
μ
PD75004, 75006, 75008
32
Serial
Interface
Shift Register (SIO)
Operation Mode
Register (CSIM)
SBI Control Register
(SBIC)
Retained
0
Undefined
0
0
0
Slave Address Register
(SVA)
Processor Clock Control
Register (PCC)
System Clock Control
Register (SCC)
Clock Output Mode
Register (CLOM)
Retained
Undefined
Clock
Generator,
Clock Output
Circuit
0
0
0
0
0
0
Interrupt
Function
Interrupt Enable Flag
(IExxx)
Interrupt Master Enable
Flag (IME)
INT0, INT1, INT2 Mode
Registers (IM0, 1, 2)
Output Buffer
0
0
0
0
0, 0, 0
0, 0, 0
Digital Port
Off
Off
Output Latch
Input/Output Mode
Register (PMGA, B, C)
Pull-Up Resistor
Specification Register
(POGA, B)
Clear (0)
0
Clear (0)
0
0
0
Bit sequential buffer (BSB0-3)
Retained
Specified
Hardware
RESET Input during Operation
RESET Input in Standby Mode
Table 8-1 Status of Each Hardware after Reset (2/2)