
53
μ
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Data Sheet U10165EJ2V0DS00
Instruction
Group
Number
of Bytes
Number
of Machine
Cycles
Addressing
Area
Mnemonic
Operand
Operation
Skip Condition
Subroutine
stack control
RETI
Note 1
1
3
μ
PD750064
MBE, RBE, 0, 0
←
(SP+1)
PC
11–0
←
(SP) (SP+3) (SP+2)
PSW
←
(SP+4) (SP+5), SP
←
SP+6
μ
PD750066, 750068
MBE, RBE, 0, PC
12
←
(SP+1)
PC
11–0
←
(SP) (SP+3) (SP+2)
PSW
←
(SP+4) (SP+5), SP
←
SP+6
μ
PD750064
0, 0, 0, 0
←
(SP+1)
PC
11–0
←
(SP) (SP+3) (SP+2)
PSW
←
(SP+4) (SP+5), SP
←
SP+6
μ
PD750066, 750068
0, 0, 0, PC
12
←
(SP+1)
PC
11–0
←
(SP) (SP+3) (SP+2)
PSW
←
(SP+4) (SP+5), SP
←
SP+6
PUSH
rp
1
1
(SP–1)(SP–2)
←
rp, SP
←
SP–2
BS
2
2
(SP–1)
←
MBS, (SP–2)
←
RBS, SP
←
SP–2
POP
rp
1
1
rp
←
(SP+1) (SP), SP
←
SP+2
BS
2
2
MBS
←
(SP+1), RBS
←
(SP), SP
←
SP+2
Interrupt
control
EI
2
2
IME (IPS.3)
←
1
IE
×××
2
2
IE
×××
←
1
DI
2
2
IME (IPS.3)
←
0
IE
×××
2
2
IE
×××
←
0
Input/output
IN
Note 2
A, PORTn
2
2
A
←
PORTn
(n = 0-6, 11)
XA, PORTn
2
2
XA
←
PORTn+1, PORTn
(n = 4)
OUT
Note 2
PORTn, A
2
2
PORTn
←
A
(n = 2-6)
PORTn, XA
2
2
PORTn+1, PORTn
←
XA
(n = 4)
CPU control
HALT
2
2
Set HALT Mode (PCC.2
←
1)
STOP
2
2
Set STOP Mode (PCC.3
←
1)
NOP
1
1
No Operation
Special
SEL
RBn
2
2
RBS
←
n
(n = 0-3)
MBn
2
2
MBS
←
n
(n = 0, 1, 15)
Notes 1.
The operations indicated with thick lines can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1, and
MBS must be set to 15.
2.