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參數(shù)資料
| 型號： | uPD750064CUA |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 4位單晶片微控制器 |
| 文件頁數(shù)： | 39/82頁 |
| 文件大?。?/td> | 460K |
| 代理商： | UPD750064CUA |
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39
μ
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
Data Sheet U10165EJ2V0DS00
Table 9-1. Status of Each Hardware After Reset (1/2)
Hardware
RESET Signal Generation
in Standby Mode
RESET Signal Generation
in Operation
Program counter (PC)
μ
PD750064
Sets the low-order 4 bits of
program memory’s address
0000H to the PC11 to PC8 and
the contents of address 0001H
to the PC7 to PC0.
Sets the low-order 4 bits of
program memory’s address
0000H to the PC11 to PC8 and
the contents of address 0001H
to the PC7 to PC0.
μ
PD750066,
750068
Sets the low-order 5 bits of
program memory’s address
0000H to the PC12 to PC8 and
the contents of address 0001H
to the PC7 to PC0.
Sets the low-order 5 bits of
program memory’s address
the contents of address 0001H
to the PC7 to PC0.
PSW
Carry flag (CY)
Held
Undefined
Skip flag (SK0 to SK2)
0
0
Interrupt status flag (IST0, IST1)
0
0
Bank enable flag (MBE, RBE)
Sets the bit 6 of program
memory’s address 0000H to
the RBE and bit 7 to the MBE.
Sets the bit 6 of program
memory’s address 0000H to
the RBE and bit 7 to the MBE.
Stack pointer (SP)
Undefined
Undefined
Stack bank select register (SBS)
1000B
1000B
Data memory (RAM)
Held
Undefined
General-purpose register (X, A, H, L, D, E, B, C)
Held
Undefined
Bank select register (MBS, RBS)
0, 0
0, 0
Basic interval
Counter (BT)
Undefined
Undefined
timer/watchdog
Mode register (BTM)
0
0
timer
Watchdog timer enable flag (WDTM)
0
0
Timer/event
Counter (T0)
0
0
counter (T0)
Modulo register (TMOD0)
FFH
FFH
Mode register (TM0)
0
0
TOE0, TOUT F/F
0, 0
0, 0
Timer/event
Counter (T1)
0
0
counter (T1)
Modulo register (TMOD1)
FFH
FFH
Mode register (TM1)
0
0
TOE1, TOUT F/F
0, 0
0, 0
Watch timer
Mode register (WM)
0
0
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