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參數(shù)資料
| 型號： | UPD72874 |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER |
| 中文描述： | IEEE1394連接的OHCI 1.1標(biāo)準(zhǔn)3PORT物理層鏈路1 -芯片的主機控制器 |
| 文件頁數(shù)： | 9/40頁 |
| 文件大小： | 297K |
| 代理商： | UPD72874 |
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Preliminary Data Sheet S15306EJ2V0DS
9
μ
PD72874
(2/2)
Name
I/O
Pin No.
I
OL
Volts(V)
Function
Block *
CLKRUN
I/O
2
PCI/Cardbus
5/3.3
PCICLK Running
as input, to determine the status
of PCLK; as output, to request starting or speeding
up clock.
Link
INTA
O
4
PCI/Cardbus
5/3.3
Interrupt
the PCI interrupt request A.
Link
PERR
I/O
41
PCI/Cardbus
5/3.3
Parity Error
is used for reporting data parity errors
during all PCI transactions, except a special cycle.
It is an output when AD0 to AD31 and PAR are both
inputs. It is an input when AD0 to AD31 and PAR
are both outputs.
Link
SERR
O
42
PCI/Cardbus
5/3.3
System Error
is used for reporting address parity
errors, data parity errors during the special cycle, or
any other system error where the effect can be
catastrophic. When reporting address parity errors,
it is an output.
Link
PRST
I
5
-
5/3.3
Reset
PCI reset
Link
PCLK
I
6
-
5/3.3
PCI Clock
33 MHz system bus clock.
Link
Remark
*: If the Link pin is pulled up, it should be connected to L_V
DD
.
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