參數(shù)資料
型號(hào)： UPD72873GC-YEB
廠商： NEC Corp.
英文描述： MOS INTEGRATED CIRCUIT
中文描述： 馬鞍山集成電路
文件頁(yè)數(shù)： 20/40頁(yè)
文件大?。?/td> 269K
代理商： UPD72873GC-YEB
Preliminary Data Sheet S15305EJ2V0DS
20
μ
PD72873
3.1.4 Offset_06 Status Register
This register tracks the status information of PCI-bus related events which are relevant to the
μ
PD72873. “Read”
and “Write” are handled somewhat differently.
Bits
R/W
Description
3-0
R
Reserved
Constant value of 0000.
4
R
New capabilities
Constant value of 1. It indicates the existence of the Capabilities List.
6,5
R
Reserved
Constant value of 00.
7
R
Fast back-to-back capable
Constant value of 1. It indicates that the
μ
PD72873, as a target,
cannot accept fast back-to-back transactions when the transactions are not to the same agent.
8
R/W
Signaled parity error
Default value of 0. It indicates the occurrence of any “Data Parity”.
0: No parity detected (default)
1: Parity detected
10,9
R
DEVSEL timing
Constant value of 01. These bits define the decode timing for DEVSEL.
0: Fast (1 cycle)
1: Medium (2 cycles)
2: Slow (3 cycles)
3: undefined
11
R/W
Signaled target abort
Default value of 0. This bit is set by a target device whenever it
terminates a transaction with “Target Abort”.
0: The
μ
PD72873 did not terminate a transaction with Target Abort
1: The
μ
PD72873 has terminated a transaction with Target Abort
12
R/W
Received target abort
Default value of 0. This bit is set by a master device whenever its
transaction is terminated with a “Target Abort”.
0: The
μ
PD72873 has not received a Target Abort
1: The
μ
PD72873 has received a Target Abort from a bus-master
13
R/W
Received master abort
Default value of 0. This bit is set by a master device whenever its
transaction is terminated with “Master Abort”. The
μ
PD72873 asserts “Master Abort” when a
transaction response exceeds the time allocated in the latency timer field.
0: Transaction was not terminated with a Master Abort
1: Transaction has been terminated with a Master Abort
14
R/W
Signaled system error
Default value of 0. It indicates that the assertion of SERR by the
μ
PD72873.
0: System error was not signaled
1: System error was signaled
15
R/W
Received parity error
Default value of 0. It indicates the occurrence of any PERR.
0: No parity error was detected
1: Parity error was detected
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