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參數(shù)資料
| 型號： | UPD7228 |
| 廠商： | NEC Corp. |
| 英文描述： | 1/8, 1/16 DUTY LCD CONTROLLER/DRIVER |
| 中文描述： | 1 / 8，1 / 16稅LCD控制器/驅(qū)動 |
| 文件頁數(shù)： | 35/64頁 |
| 文件大?。?/td> | 314K |
| 代理商： | UPD7228 |
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Data Sheet S10299EJ4V0DS00
35
μ
PD16434
7. STANDBY MODE
The
μ
PD16434 offers the standby mode in order to reduce the power consumption, when displaying operation is
not necessary.
The standby mode is set, by executing the STOP command. The standby mode is actually set, when the /BUSY
signal is set to high after the STOP command is executed. In the standby mode, the
μ
PD16434 stops supplying the
CLOCK signal to the LCD timing control circuit and the clock control circuit by internally masking the CLOCK signal. In
addition, the
μ
PD16434 initializes the data processing mode to the auto-increment (I
1
I
0
= 00) write mode. However, no
other modes are affected by RESET operation, so that the interface mode and the display mode will be retained. The
standby mode is cleared when a byte of data (command or data) is input, or when the RESET signal falls. However, the
processing necessary during the standby mode and operation after clearing the standby mode differ, depending on which
method is used.
In addition, the CLOCK signal to the
μ
PD16434 can be stopped during the standby mode. In this case, the power
consumption can be further reduced, compared to when the CLOCK is only internally masked.
7.1 Clearing Standby Mode
(1) Clearing standby mode by writing a byte of data
If the previous operation modes (except the data processing mode), used before entering the standby mode,
needs to be maintained, the standby mode can be cleared by writing a byte of data (command or data).
In the serial interface mode, the standby mode is cleared, when writing 8 bits of serial data is completed (at the
rising edge of the 8th /SCK). In the parallel interface, the standby mode is cleared, when writing the second 4-bit
data is completed (at the rising edge of the 2nd /STB).
When the chip address selection function is used in the serial interface mode, if /CS is set to high in the standby
mode, the first 8-bit data, after /CS is set to low, is used as the chip address information, when the standby mode
is cleared. Therefore, the standby mode is cleared, when writing the next 8-bit data is completed.
Remark
During the standby mode, the clock necessary for driving the LCD by alternating current is stopped.
Therefore, the LCD drive signal level, before entering the standby mode, is maintained in the standby
mode. This means that a DC voltage remains applied to the LCD in the standby mode. To avoid this,
control the V
LC5
pin voltage using the CPU output port, as shown in Figure7–1, and output a high
level from the output port, before executing the STOP command, to eliminate voltage differential
between the V
DD
and V
LC5
.
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