參數(shù)資料
型號： UPD720133
廠商： NEC Corp.
英文描述： MOS Integrated Circuit
中文描述： 馬鞍山集成電路
文件頁數(shù)： 28/36頁
文件大小： 409K
代理商： UPD720133
S17100JJ2V0DS
28
μ
PD720133
USB reset sequence from suspend state on full-speed system bus
t
SCA
t
CKO
t
SCS
t
FCA
t
DRS
Chirp K device out
FSJ
FSJ
Pull-up is active.
T
0
USB bus
USB reset sequence from suspend state on high-speed system bus
t
SCA
t
CKO
t
SCS
t
FCA
Chirp K device out
Reversion to high-speed mode
FSJ
Pull-up is active.
T
0
USB bus
t
SSC
t
CSI
t
RHA
t
FSC
Chrip state from host/hub
Reset Complete
K
K
J
K
K
J
J
J
USB suspend and resume on full-speed system bus
USB bus
FSJ
FSJ
FSK
FS EOP
t
SUS
Power will be down
Note time required to relock PLL
and stabilize oscillator.
t
SPD
USB suspend and resume on high-speed system bus
USB bus
FSJ
FSK
High-speed packet
t
SPD
t
SUS
Power will be down
Note time required to relock PLL
and stabilize oscillator.
t
CSR
Reversion to full-speed mode
t
RHS
High-speed packet
Reversion to high-speed mode
T
0
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