參數(shù)資料
型號: UPD720122
廠商: NEC Corp.
英文描述: MOS Integrated Circuit
中文描述: 馬鞍山集成電路
文件頁數(shù): 10/82頁
文件大?。?/td> 650K
代理商: UPD720122
Data Sheet S16685EJ2V0DS
10
μ
PD720122
(2/2)
Pin Name
I/O
Buffer Type
Active Level
Function
RSDM
O
USB full speed D- O
USB’s full speed D
signal
M(1:0)
I
5 V tolerant Input
Function mode setting
VBUS
I
5 V tolerant Input
Note
VBUS monitoring
AV
DD
, PV
DD
3.3 V
DD
for Analog circuit
V
DD
3.3 V
DD
AV
SS
, PV
SS
V
SS
for Analog circuit
V
SS
, GND
V
SS
NC
Not connect
Reserved
Not used
Note
VBUS pin may be used to monitor for VBUS line even if V
DD
, AV
DD
, and PV
DD
are shut off. System must
ensure that the input voltage level for VBUS pin is less than 3.0 V due to the absolute maximum rating is not
exceeded.
“5 V tolerant“ means that the buffer is 3.3 V buffer with 5 V tolerant circuit.
Remark
The operation mode of the BIU can be set by external pins, as shown below. Fix external pins (M1 and M0) when
using them.
Pin
M1
M0
BIU Operation Mode
Outline
0
0
16-bit mode
(Function 1)
A 16-bit CPU bus and an external local bus dedicated to data transfer for bulk IN/OUT can
be used in this mode. The internal register length is 16 bits.
0
1
8-bit mode
(Function 2)
Multiplexed bus mode of 8-bit address bus and 8-bit data bus.
The register length is 8 bits only in this mode (registers can only be accessed in byte units).
Therefore, the address space in this mode differs from that in the other modes.
The active levels of some external local bus control pins can be changed by the Active pin.
1
0
16-bit mix mode
(Function 3)
Multiplexed bus mode of 8-bit address bus and 16-bit data bus.
The internal register length is 16 bits.
The active levels of some external local bus control pins can be changed by the Active pin.
1
1
Setting prohibited
(Function 4)
Setting prohibited
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