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User’s Manual U18854EJ2V0UD
16
18.5.2
Debug trap ...............................................................................................................................855
18.6
External Interrupt Request Input Pins (NMI and INTP0 to INTP14) ................................. 857
18.6.1
Noise elimination .....................................................................................................................857
18.6.2
Edge detection.........................................................................................................................857
18.7
Interrupt Acknowledge Time of CPU .................................................................................. 867
18.8
Periods in Which Interrupts Are Not Acknowledged by CPU .......................................... 868
18.9
Cautions ................................................................................................................................ 868
CHAPTER 19 KEY INTERRUPT FUNCTION ..................................................................................... 869
19.1
Function................................................................................................................................. 869
19.2
Register ................................................................................................................................. 870
19.3
Cautions ................................................................................................................................ 870
CHAPTER 20 STANDBY FUNCTION .................................................................................................. 871
20.1
Overview................................................................................................................................ 871
20.2
Registers ............................................................................................................................... 873
20.3
HALT Mode............................................................................................................................ 878
20.3.1
Setting and operation status ....................................................................................................878
20.3.2
Releasing HALT mode.............................................................................................................878
20.4
IDLE1 Mode ........................................................................................................................... 880
20.4.1
Setting and operation status ....................................................................................................880
20.4.2
Releasing IDLE1 mode ............................................................................................................880
20.5
IDLE2 Mode ........................................................................................................................... 882
20.5.1
Setting and operation status ....................................................................................................882
20.5.2
Releasing IDLE2 mode ............................................................................................................882
20.5.3
Securing setup time when releasing IDLE2 mode ................................................................... 884
20.6
STOP Mode............................................................................................................................ 885
20.6.1
Setting and operation status ....................................................................................................885
20.6.2
Releasing STOP mode ............................................................................................................885
20.6.3
Securing oscillation stabilization time when releasing STOP mode .........................................887
20.7
Subclock Operation Mode ................................................................................................... 888
20.7.1
Setting and operation status ....................................................................................................888
20.7.2
Releasing subclock operation mode ........................................................................................888
20.8
Sub-IDLE Mode ..................................................................................................................... 890
20.8.1
Setting and operation status ....................................................................................................890
20.8.2
Releasing sub-IDLE mode .......................................................................................................891
CHAPTER 21 RESET FUNCTIONS ..................................................................................................... 893
21.1
Overview................................................................................................................................ 893
21.2
Registers to Check Reset Source....................................................................................... 894
21.3
Operation............................................................................................................................... 895
21.3.1
Reset operation via RESET# pin .............................................................................................895
21.3.2
Reset operation by watchdog timer 2.......................................................................................897
21.3.3
Reset operation by power-on clear circuit................................................................................898
21.3.4
Reset operation by low-voltage detector..................................................................................898
21.3.5
Reset operation by clock monitor.............................................................................................898
21.4
Operation After Reset Release............................................................................................ 899