參數(shù)資料
型號(hào)： UPD70F3134AGJ-UEN
廠商： NEC Corp.
英文描述： 32-Bit Single-Chip Microcontrollers
中文描述： 32位單芯片微控制器
文件頁(yè)數(shù)： 39/99頁(yè)
文件大小： 528K
代理商： UPD70F3134AGJ-UEN
CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
Application Note U17121EJ1V1AN
39
3.4.6 PCI_INT_CTL register
The PCI_INT_CTL register shows the interrupt sources of the PCI bus error interrupt (O_PCIHOST_INT) and
controls masking and clearing of these interrupts.
This function is used only for debugging and is not used in normal operation.
After reset: 000x0F00H R/W Offset address: 18H
31
20 19 18 17 16 15
12 11 10
9
8
7
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
C
C
C
C
0
0
0
0
M
M
M
M
0
0
0
0
S
P
M
T
Bit Name
R/W
Function
CLR_SERR
W
Clears the PCI bus system error (SERR# reception) interrupt.
1: Cleared
CLR_PERR
W
Clears the PCI bus parity error (PERR# reception) interrupt.
1: Cleared
CLR_MAB
W
Clears the PCI bus master abort interrupt.
1: Cleared
CLR_TAB
W
Clears the PCI bus target abort interrupt.
1: Cleared
MSK_SERR
R/W
Sets the mask status of the PCI bus system error (SERR# reception) interrupt.
0: Not masked
1: Masked
MSK_PERR
R/W
Sets the mask status of the PCI bus parity error (PERR# reception) interrupt.
0: Not masked
1: Masked
MSK_MAB
R/W
Sets the mask status of the PCI bus master abort interrupt.
0: Not masked
1: Masked
MSK_TAB
R/W
Sets the mask status of the PCI bus target abort interrupt.
0: Not masked
1: Masked
SERR
R
Detects the occurrence status of a PCI bus system error (SERR# reception).
1: System error occurred
PERR
R
Detects the occurrence status of the PCI bus parity error (PERR# reception).
1: Parity error occurred
MABORT
R
Detects the occurrence status of the PCI bus master abort.
1: Master abort occurred
TABORT
R
Detects the occurrence status of the PCI bus target abort.
1: Target abort occurred
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參數(shù)描述
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