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參數(shù)資料
| 型號： | UPD70F3008GJ-33-8EU |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 220K |
| 代理商： | UPD70F3008GJ-33-8EU |
PD70F3008
10
(2/3)
Pin Name
I/O
Function
Alternate Function
HLDAK
Output
Bus hold acknowledge output.
P95
HLDRQ
Input
Bus hold request input.
P96
SO0
Input
Serial transmit data output from CSI0 to CSI3 (3-wire).
P30/TXD
SO1
P33
SO2
P120
SO3
P123
SI0
Input
Serial receive data input to CSI0 to CSI3 (3-wire).
P31/RXD
SI1
P34
SI2
P121
SI3
P124
SCK0
I/O
Serial clock I/O from/to CSI0 to CSI3 (3-wire).
P32
SCK1
P35
SCK2
P122
SCK3
P125
TXD
Output
Serial transmit data output from UART.
P30/SO0
RXD
Input
Serial receive data input to UART.
P31/SI0
PWM0 to PWM3
Output
Pulse signal output from PWM.
P100 to P103
WRL
Output
Lower byte of external data bus write strobe signal output.
P90/LBEN
WRH
Higher byte of external data bus write strobe signal output.
P92/R/W
RD
Output
External data bus read strobe signal output.
P93/DSTB
ANI0 to ANI7
Input
Analog input to A/D converter.
P70 to P77
ANI8 to ANI15
P80 to P87
RTP0 to RTP7
Output
Real time output port.
P130 to P137
CLO
Output
System clock output (with frequency division function).
P127
CKSEL
Input
Input to specify clock generator operation mode.
–
PLLSEL
Input
Input to specify the number of PLL multiplication.
–
CLKOUT
Output
System clock output.
–
WAIT
Input
Control signal input inserting wait state to bus cycle.
–
MODE0 to MODE2
Input
Specifies operation mode.
–
RESET
Input
System reset input.
–
X1
Input
System clock oscillator connecting pins. Supply external clock to X1.
–
X2
–
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD70F3008YGJ-16-8EU | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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| UPD70F3015BGC-8EU | 制造商:NEC 制造商全稱:NEC 功能描述:32-BIT SINGLE-CHIP MICROCONTROLLER |
| UPD70F3015BGC-8EU-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD70F3015BY | 制造商:NEC 制造商全稱:NEC 功能描述:32-BIT SINGLE-CHIP MICROCONTROLLER |
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