![](http://datasheet.mmic.net.cn/370000/UPD703201_datasheet_16740720/UPD703201_81.png)
Preliminary Product Information U15436EJ1V0PM
81
μ
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(c) Write cycle (CLKOUT asynchronous): In separate bus mode
(T
A
=
–
40 to +85
°
C, V
DD
= AV
DD
= EV
DD
= V
DD
BU = 2.2 to 2.7 V, V
SS
= AV
SS
= EV
SS
= V
SS
BU = 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to WRm
↓
)
t
SAW
<72>
T
–
15
ns
Address hold time (from WRm
↑
)
t
HAW
<73>
0.5T
–
10
ns
WRm low-level width
t
WWRL
<74>
(0.5 + n) T
–
10
ns
Data output time from WRm
↓
t
DOSDW
<75>
–
5
ns
Data setup time (to WRm
↑
)
t
SOSDW
<76>
(0.5 + n) T
–
10
ns
Data hold time (from WRm
↑
)
t
HOSDW
<77>
0.5T
–
10
ns
Data setup time (to address)
t
SAOD
<78>
T
–
25
ns
t
SWRWT1
<79>
20
ns
WAIT setup time (to WRm
↓
)
t
SWRWT2
<80>
nT
–
20
ns
t
HWRWT1
<81>
0
ns
WAIT hold time (from WRm
↓
)
t
HWRWT2
<82>
nT
ns
t
SAWT1
<83>
T
–
20
ns
WAIT setup time (to address)
t
SAWT2
<84>
(1 + n) T
–
20
ns
t
HAWT1
<85>
T
ns
WAIT hold time (from address)
t
HAWT2
<86>
(1 + n) T
ns
Remarks 1.
m = 0, 1
T = 1/f
CPU
(f
CPU
: CPU operation clock frequency)
n: Number of wait clocks inserted in bus cycle
The sampling timing changes when a programmable wait is inserted.
The values in the above specifications are the values for when clocks with a 1:1 duty ratio are input
from X1.
2.
3.
4.
(d) Write cycle (CLKOUT synchronous): In separate bus mode
(T
A
=
–
40 to +85
°
C, V
DD
= AV
DD
= EV
DD
= V
DD
BU = 2.2 to 2.7 V, V
SS
= AV
SS
= EV
SS
= V
SS
BU = 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay time from CLKOUT
↑
to address, CS t
DKSA
<87>
0
19
ns
Delay time from CLKOUT
↑
to data output
t
DKSD
<88>
0
19
ns
Delay time from CLKOUT
↑↓
to WRm
t
DKSW
<89>
0
19
ns
WAIT setup time (to CLKOUT
↑
)
t
SWTK
<90>
15
ns
WAIT hold time (from CLKOUT
↑
)
t
HKWT
<91>
5
ns
Remarks 1.
m = 0, 1
The values in the above specifications are the values for when clocks with a 1:1 duty ratio are input
from X1.
2.