參數(shù)資料
型號(hào)： UPD4991A
廠商： NEC Corp.
英文描述： 4-BIT PARALLEL I/O CALENDAR CLOCK
中文描述： 4位并行I / O日歷鐘
文件頁(yè)數(shù)： 22/32頁(yè)
文件大?。?/td> 133K
代理商： UPD4991A
μ
PD4991A
22
Fig. 6 TP
1
Output Status (without AUTO RESET)
TP
2
SET (MODE = 0 * 1 1 B)
The TP
2
pin outputs an interval timer signal.
This signal is cyclically output.
The cycle at which the interval timer signal is output can be selected between 0.1 s, 1 s, 10 s, 30 s, and 60 s,
depending on the contents indicated by the TP
2
CONTROL REGISTER. Note, however, that the 0.1-s cycle
does not last exactly for 0.1 second, but that five 0.1-s cycles are equivalent to one 0.5 second.
If
±
30 s ADJ, RESET is executed in mode (0, *, 1, 1), an error occurs in the cycle.
Fig. 7 TP
2
Output Waveform
REPEAT output
1-shot output
T
T
T
START
30.5 s
T
T
30.5 s
μ
START
T
30.5 s
TP
1
2048 Hz
1 Hz
~
"H"
→
"L"
1 pulse
ALARM ENABLE
Alarm coincidence flag reset
Output status enabled
Alarm coincidence
Alarm does not
coincide
Alarm coincidence
flag reset
Alarm coincidence
flag set
Alarm
coincidence
flag ON
Alarm
coincidence
flag OFF
Alarm
coincidence
flag ON
30.5 s
Alarm coincidence
Alarm does not
coincide
Output status
disabled
Output status
enabled
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