參數資料
型號: UPD4564163
廠商: Elpida Memory, Inc.
英文描述: 64M-bit Synchronous DRAM 4-bank, LVTTL
中文描述: 6400位同步DRAM 4銀行,LVTTL
文件頁數: 32/85頁
文件大?。?/td> 919K
代理商: UPD4564163
Data Sheet E0149N10
32
μ
PD4564441, 4564841, 4564163
12.2 Precharge Termination
12.2.1 Precharge Termination in READ Cycle
During a read cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after t
RP
from the precharge command.
To issue a precharge command, t
RAS
must be satisfied.
When /CAS latency is 2, the read data will remain valid until one clock after the precharge command.
Read
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 2
Q1
DQ
Command
Q2
Q3
Q4
ACT
t
RP
PRE
Hi-Z
(t
RAS
must be satisfied)
When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Read
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 3
DQ
Command
Q1
Q2
Q3
ACT
t
RP
PRE
Hi-Z
T8
Q4
(t
RAS
must be satisfied)
相關PDF資料
PDF描述
UPD4564163G5 64M-bit Synchronous DRAM 4-bank, LVTTL
UPD4564441 64M-bit Synchronous DRAM 4-bank, LVTTL
UPD4564841 64M-bit Synchronous DRAM 4-bank, LVTTL
UPD485505 LINE BUFFER 5K-WORD BY 8-BIT
UPD485505G-25 LINE BUFFER 5K-WORD BY 8-BIT
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