參數(shù)資料
型號(hào)： UPD45128163G5-A10LI-9JF
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
中文描述： 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝： PLASTIC, TSOP2-54
文件頁(yè)數(shù)： 31/86頁(yè)
文件大小： 785K
代理商： UPD45128163G5-A10LI-9JF
Data Sheet E0346N10 (Ver. 1.0)
31
μ
PD45128163-I
12.2.2 Precharge Termination in WRITE Cycle
During a write cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after t
RP
from the precharge command.
To issue a precharge command, t
RAS
must be satisfied.
When /CAS latency is 2, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
WRITE
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 2
DQ
Command
D1
D2
D3
ACT
DQM
t
RP
PRE
Hi-Z
D4
D5
(t
RAS
must be satisfied)
When /CAS latency is 3, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
WRITE
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 3
DQ
Command
D1
D2
D3
ACT
DQM
t
RP
PRE
Hi-Z
D5
T8
D4
(t
RAS
must be satisfied)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD45128163G5-A75-9JF 制造商:Elpida Memory Inc 功能描述:8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
UPD45128841G5-A75-9JF 制造商:NEC Electronics Corporation 功能描述:SDRAM, 16M x 8, 54 Pin, Plastic, TSOP
UPD4516161AG5A109NF 制造商:NEC Electronics Corporation 功能描述:
UPD4516161AG5-A10-9NF 制造商:NEC Electronics Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP
UPD4528BC 制造商:Panasonic Industrial Company 功能描述:IC
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