參數(shù)資料
型號(hào)： UPD44165364F5-E50-EQ1
廠商： NEC Corp.
英文描述： 18M-BIT QDRII SRAM 4-WORD BURST OPERATION
中文描述： 1800萬(wàn)位推出QDRII SRAM的4個(gè)字爆發(fā)運(yùn)作
文件頁(yè)數(shù)： 9/32頁(yè)
文件大?。?/td> 392K
代理商： UPD44165364F5-E50-EQ1
9
Data Sheet M15825EJ7V
1
DS
μ
PD44165084, 44165184, 44165364
Byte Write Operation
[
μ
PD44165084]
Operation
K
/K
/NW0
/NW1
Write D0 to D7
L
→
H
–
–
0
0
L
→
H
–
0
0
Write D0 to D3
L
→
H
–
0
1
L
→
H
–
0
1
Write D4 to D7
L
→
H
–
1
0
L
→
H
–
1
0
Write nothing
L
→
H
–
1
1
L
→
H
1
1
Remarks 1.
H : High level, L : Low level,
→
: rising edge.
2.
Assumes a WRITE cycle was initiated. /NW0 and /NW1 can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[
μ
PD44165184]
Operation
K
/K
/BW0
/BW1
Write D0 to D17
L
→
H
–
–
0
0
L
→
H
–
0
0
Write D0 to D8
L
→
H
–
0
1
L
→
H
–
0
1
Write D9 to D17
L
→
H
–
1
0
L
→
H
–
1
0
Write nothing
L
→
H
–
1
1
L
→
H
1
1
Remarks 1.
H : High level, L : Low level,
→
: rising edge.
2.
Assumes a WRITE cycle was initiated. /BW0 and /BW1 can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[
μ
PD44165364]
Operation
K
/K
/BW0
/BW1
/BW2
/BW3
Write D0 to D35
L
→
H
–
–
0
0
0
0
L
→
H
–
0
0
0
0
Write D0 to D8
L
→
H
–
0
1
1
1
L
→
H
–
0
1
1
1
Write D9 to D17
L
→
H
–
1
0
1
1
L
→
H
–
1
0
1
1
Write D18 to D26
L
→
H
–
1
1
0
1
L
→
H
–
1
1
0
1
Write D27 to D35
L
→
H
–
1
1
1
0
L
→
H
–
1
1
1
0
Write nothing
L
→
H
–
1
1
1
1
L
→
H
1
1
1
1
Remarks 1.
H : High level, L : Low level,
→
: rising edge.
2.
Assumes a WRITE cycle was initiated. /BW0 to /BW3 can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
相關(guān)PDF資料
PDF描述
UPD44165364F5-E60-EQ1 18M-BIT QDRII SRAM 4-WORD BURST OPERATION
UPD44324082F5-E37-EQ2 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44324082F5-E37-EQ2-A 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44324082F5-E40-EQ2-A 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44324082F5-E50-EQ2-A 36M-BIT DDRII SRAM 2-WORD BURST OPERATION
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