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參數(shù)資料
| 型號(hào)： | UPD43257BGU-85LL |
| 廠商： | NEC Corp. |
| 英文描述： | 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT |
| 中文描述： | 256K位CMOS靜態(tài)RAM 32K的詞8位 |
| 文件頁(yè)數(shù)： | 13/20頁(yè) |
| 文件大小： | 157K |
| 代理商： | UPD43257BGU-85LL |
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Data Sheet M10693EJ7V0DS00
13
μ
PD43257B
Write Cycle Timing Chart 3 (CE2 Controlled)
t
WC
t
AS
t
CW2
t
DW
t
DH
Data in
High impedance
Address (Input)
CE2 (Input)
I/O (Input)
High
impedance
/CE1 (Input)
t
CW1
t
AW
t
WP
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. When I/O pins are in the output state, therefore the input signals must not be applied
to the output.
Remark
Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
#
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