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參數(shù)資料
| 型號： | UPD43257BCZ-70LL |
| 廠商： | NEC Corp. |
| 英文描述： | 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT |
| 中文描述： | 256K位CMOS靜態(tài)RAM 32K的詞8位 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 157K |
| 代理商： | UPD43257BCZ-70LL |
Data Sheet M10693EJ7V0DS00
15
μ
PD43257B
Data Retention Timing Chart
(1) /CE1 Controlled
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
V
CC
/CE1
/CE1
≥
V
CC
– 0.2 V
GND
4.5 V
t
CDR
Data retention mode
t
R
Remark
On the data retention mode by controlling /CE1, the input level of CE2 must be CE2
≥
V
CC
0.2 V or
CE2
≤
0.2 V. The other pins (Address, I/O, /WE) can be in high impedance state.
(2) CE2 Controlled
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
V
CC
CE2
CE2
≤
0.2 V
GND
4.5 V
t
CDR
Data retention mode
t
R
Remark
On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE) can be in
high impedance state.
#
#
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