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參數(shù)資料
| 型號(hào)： | UPD3719 |
| 廠商： | NEC Corp. |
| 英文描述： | 10600 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR |
| 中文描述： | 10600像素× 3彩色CCD線性圖像傳感器 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 147K |
| 代理商： | UPD3719 |
μ
PD3719
5
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C)
Parameter
Symbol
Ratings
Unit
Output drain voltage
V
OD
–0.3 to +16
V
Reset drain voltage
V
RD
–0.3 to +16
V
Shift register clock voltage
V
φ
1
, V
φ
2
–0.3 to +8
V
Reset gate clock voltage
V
φ
RB
–0.3 to +8
V
Reset feed-through level clamp clock voltage
V
φ
CLB
–0.3 to +8
V
Transfer gate clock voltage
V
φ
TG
–0.3 to +8
V
Operating ambient temperature
T
A
–25 to +60
°
C
Storage temperature
T
stg
–40 to +100
°
C
Caution
Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (T
A
= +25
°
C)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Output drain voltage
V
OD
14.0
15.0
16.0
V
Reset drain voltage
V
RD
14.0
V
OD
V
OD
V
Shift register clock high level
V
φ
1H
, V
φ
2H
4.5
5.0
5.5
V
Shift register clock low level
V
φ
1L
, V
φ
2L
–0.3
0
+0.5
V
Reset gate clock high level
V
φ
RBH
4.5
5.0
5.5
V
Reset gate clock low level
V
φ
RBL
–0.3
0
+0.5
V
Reset feed-through level clamp clock high level
V
φ
CLBH
4.5
5.0
5.5
V
Reset feed-through level clamp clock low level
V
φ
CLBL
–0.3
0
+0.5
V
Transfer gate clock high level
V
φ
TGH
4.5
V
φ
1H
Note
V
φ
1H
Note
V
Transfer gate clock low level
V
φ
TGL
–0.3
0
+0.3
V
Data rate
f
φ
RB
–
1
2
MHz
Note
When Transfer gate clock high level (V
φ
TGH
) is higher than Shift register clock high level (V
φ
1H
), Image lag
can increase.
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相關(guān)代理商/技術(shù)參數(shù) |
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| UPD3720ACY | 制造商:NEC 制造商全稱:NEC 功能描述:2700 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR |
| UPD3725A | 制造商:NEC 制造商全稱:NEC 功能描述:5000-BIT x 3 CCD COLOR LINEAR IMAGE SENSOR |
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