
CHAPTER 5 MEMORY MANAGEMENT SYSTEM
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5.3.4 LCD Space
This space is used to access the external LCD controller.
All data that is accessed via this space is inverted-bit data.
The LCD space is used exclusively from the high-speed system bus memory space. To switch between these
two types of space, set the ISAM/LCD bit in BCUCNTREG1.
5.3.5
DRAM Space
The DRAM space differs depending on the data bus’ bit width and the capacity of the DRAM being used.
The data bus’ bit width is set via the DBUS32 pin.
The DRAM capacity is set via the BCUCNTREG1’s DRAM64 bit.
The physical addresses of the DRAM space are listed below.
Table 5-11. DRAM Addresses (when using 16-bit data bus)
Physical address
When using 16-Mbit DRAM
When using 64-Mbit DRAM
0x03FF FFFF to 0x0200 0000
DRAM space reserved for future use
DRAM space reserved for future use
0x01FF FFFF to 0x0180 0000
Bank 3 (MRAS[3]#/UUCAS#)
0x017F FFFF to 0x0100 0000
Bank 2 (MRAS[2]#/ULCAS#)
0x00FF FFFF to 0x0080 0000
Bank 1 (MRAS[1]#)
0x007F FFFF to 0x0060 0000
Bank 3 (MRAS[3]#/UUCAS#)
Bank 0 (MRAS[0]#)
0x005F FFFF to 0x0040 0000
Bank 2 (MRAS[2]#/ULCAS#)
0x003F FFFF to 0x0020 0000
Bank 1 (MRAS[1]#)
0x001F FFFF to 0x0000 0000
Bank 0 (MRAS[0]#)
Table 5-12. DRAM Addresses (when using 32-bit data bus)
Physical address
When using 16-Mbit DRAM
When using 64-Mbit DRAM
0x03FF FFFF to 0x0200 0000
DRAM space reserved for future use
DRAM space reserved for future use
0x01FF FFFF to 0x0180 0000
Bank 1 (MRAS[1]#)
0x017F FFFF to 0x0100 0000
0x00FF FFFF to 0x0080 0000
Bank 0 (MRAS[0]#)
0x007F FFFF to 0x0060 0000
Bank 1 (MRAS[1]#)
0x005F FFFF to 0x0040 0000
0x003F FFFF to 0x0020 0000
Bank 0 (MRAS[0]#)
0x001F FFFF to 0x0000 0000