參數(shù)資料
型號(hào)： UPD17073
廠商： NEC Corp.
英文描述： FILTER BAND PASS 5.8GHZ SMD
中文描述： 4位單芯片的數(shù)字調(diào)諧系統(tǒng)硬件單片機(jī)
文件頁(yè)數(shù)： 170/226頁(yè)
文件大?。?/td> 1250K
代理商： UPD17073
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μ
PD17072,17073
170
19.2 Halt Function
19.2.1 General
The halt function is to stop the operation clock of the CPU by executing the “HALT h” instruction.
When this instruction has been executed, the program is stopped and is not executed unless the halt status is
released. Therefore, the current consumption of the device is reduced by the operating current of the CPU in the halt
status.
The halt status is released by key input, basic timer 0, or interrupt.
The releasing condition is specified by the operand “h” of the HALT h instruction.
The HALT h instruction is valid regardless of the input level of the CE pin.
19.2.2 Halt status
In the halt status, all the operations of the CPU are stopped. In other words, the program execution is stopped
by the “HALT h” instruction. However, the peripheral hardware retains the status set before the HALT h instruction
is executed.
For the operation of each peripheral hardware, refer to
19.4 Device Operations in Halt and Clock Stop Statuses
.
19.2.3 Halt release condition
Figure 19-2 shows the halt release conditions.
The halt release condition is set by 4-bit data that is specified by the operand “h” of the HALT h instruction.
The halt status is released when the condition specified as “1” in operand “h” is satisfied.
When the halt status has been released, program execution is started from the instruction next to "HALT h"
instruction.
If two or more release conditions are specified, the halt status is released if any one of the specified conditions
has been satisfied.
When the device has been reset (by means of power-ON reset or CE reset), the halt status is released, and the
appropriate reset operation is performed.
If 0000B is set as the halt release condition “h”, no release condition is set. In this case, the halt status is released
when the device is reset (power-ON reset or CE reset).
Figure 19-2. Halt Release Condition
Operand
b
1
b
2
b
3
b
0
Releases if high level is input to port 1A
Releases if basic timer 0 carry FF is set (1)
Undefined (Fix this bit to "0".)
Releases when interrupt request flag and interrupt enable flag are set
(When executing EI and DI instructions)
HALT h (4 bits)
0: Does not release halt status even if condition is satisfied
1: Releases halt status if condition is satisfied
Sets halt status release condition
相關(guān)PDF資料
PDF描述
UPD17072GB 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
UPD17215CT 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER
UPD17217GT 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD17073GB 制造商:NEC 制造商全稱:NEC 功能描述:4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
UPD17073GB-XXX-1A7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller
UPD17073GB-XXX-9EU 制造商:未知廠家 制造商全稱:未知廠家 功能描述:4-Bit Microcontroller
UPD1708AG-011 制造商:NEC 制造商全稱:NEC 功能描述:PLL FREQUENCY SYNTHESIZER AND CONTROLLER FOR FM/MW/LW TUNER
UPD1708AG-011-00 制造商:NEC 制造商全稱:NEC 功能描述:PLL FREQUENCY SYNTHESIZER AND CONTROLLER FOR FM/MW/LW TUNER
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