- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383979 > UPD16682N (NEC Corp.) 1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM PDF資料下載
參數(shù)資料
| 型號： | UPD16682N |
| 廠商： | NEC Corp. |
| 英文描述： | 1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| 中文描述： | 1 / 65稅LCD控制器/驅(qū)動器，片內(nèi)RAM |
| 文件頁數(shù)： | 16/56頁 |
| 文件大?。?/td> | 435K |
| 代理商： | UPD16682N |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
Data Sheet S13368EJ3V0DS00
16
μ
PD16682
6. DISPLAY DATA RAM
6.1 Display Data RAM
This is the RAM that is used to store the display’s dot data. The RAM configuration is 65 (8 pages x 8 bits + 1) x
132 bits. Any specified bit can be accessed by selecting the corresponding page address and column address.
As is shown in Figure 6
1 below, the display data (D
7
to D
0
) from the MPU corresponds to the common direction in
the LCD, so that if a multiple set of
μ
PD16682 chips is used, there are fewer constraints on transfers of display data
and relatively more freedom for display configurations.
The MPU accesses the display data RAM for read/write operations via the I/O buffer, and these operations are
independent of the LCD driver signal read operations. Therefore, there are absolutely no adverse effects (such as
flicker) in the display when display data RAM is accessed asynchronously in relation to the LCD contents.
Figure 6
1. LCD Data and LCD Display
LCD data
LCD display
D
0
0
1
1
1
0
COM
0
D
1
1
0
0
0
0
COM
1
D
2
0
0
0
0
0
COM
2
D
3
0
1
1
1
0
COM
3
D
4
1
0
0
0
0
COM
4
...
...
6.2 Page Address Circuit
The page address set command specifies the page address in the display data RAM, as is shown in Figure 6
2. To
access a different page, simply specify a different page address using this command.
Page address 8 (D
3
,D
2
,D
1
,D
0
= 1,0,0,0) is a RAM area that is used exclusively for indicator, so only display data D
0
is valid.
6.3 Column Address Circuit
The column address set command specifies the column address in the display data RAM, as is shown in Figure
6
2. The specified column address is incremented each time a display data read or write command is input, so the
MPU is able to successively access display data.
Incrementation of the column address stops at 83H. The column address and page address are mutually
independent, which means that to switch from column 83H on page 0 to column 00H on page 1, both the page
address and column address must be separately specified again.
Also, as is shown in Table 6
1, the ADC command (segment driver direction select command) can be used to invert
the correspondence between the display data RAM’s column address and segment output. This reduces the number
of IC layout constraints that are imposed when setting up the LCD module.
Table 6
1. Relation between Display Data RAM Column Address and Segment Output
SEG Output
SEG
0
SEG
131
ADC
“0”
00H
→
Column Address
→
83H
(D
0
)
“1”
83H
←
Column Address
←
00H
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD16682P | 1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| UPD16682W | 1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| UPD16700 | 256-OUTPUT TFT-LCD GATE DRIVER |
| UPD16700N | DUSTCAP, METAL SZ22; Material:Zinc Alloy; Colour:Nickel Plated; Connector shell size:22; Voltage rating, AC:750V; Series:TRIM TRIO |
| UPD16803 | MONOLITHIC DUAL H BRIDGE DRIVER CIRCUIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD16682P | 制造商:NEC 制造商全稱:NEC 功能描述:1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| UPD16682P-001 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| UPD16682P-002 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| UPD16682P-003 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| UPD16682P-004 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。