
Data Sheet S13780EJ1V0DS00
2
μ
PD16664
1. PIN NAME
Classification
Pin Name
Note
I/O
Function
CPU interface
V
CC2
D
0
-D
15
A
0
-A
16
/CS
/OE
/WE
/UBE
RDY
I/O
I
I
I
I
I
O
Data bus: 16 bits
Address bus: 17 bits
Chip select
Read signal
Write signal
Upper byte enable
Ready signal to CPU (“H”: ready)
Control signals
V
CC2
PL0
PL1
DIR
DMODE
CMODE0,1
MS
BMODE
/REFRH
TEST
/RESET
/DOFF
OSC1
OSC2
I
I
I
I
I
I
I
I/O
I
I
I
–
–
Specifies LSI layout position (No. 0 to 3)
Specifies LSI layout position (No. 0 to 3)
Specifies liquid crystal panel layout position
Duty selection (“H” = 1/128 duty, “L” =1/160 duty)
Number of column outputs selection
Master/slave selection (“H”: master mode)
Data bus bit selection (“H” = 8 bits, “L” = 16 bits)
Self-diagnosis reset pin (wired-OR connection)
Test pin (“H” = test mode, with pull-down resistor)
Reset signal
Display OFF input signal
External resistor pin for oscillator
External resistor pin for oscillator
V
CC1
STB
/FRM
PULSE
L1
L2
/DOUT
I/O
I/O
I/O
I/O
I/O
O
Column drive signal (MS pin “H” = output, MS pin “L” = input)
Frame signal (MS pin “H” = output, MS pin “L” = input)
25-level pulse modulation clock
Row driver drive level select signal (first line)
Row driver drive level select signal (second line)
Display OFF output signal
Liquid crystal drive
Y
1
-Y
208
O
Liquid crystal drive output
Power
GND
V
CC1
V
CC2
V
0
V
1
V
2
–
–
–
–
–
–
Ground (two pins for V
CC1
system, three pins for V
CC2
system)
Power supply for liquid crystal drive and row driver interface
Power supply for logic
Liquid crystal drive analog power
Liquid crystal drive analog power
Liquid crystal drive analog power
Note
V
CC2
system pins : D
0
to D
15
, A
0
to A
16
, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR,
OSC1, OSC2, /RESET, /DOFF, TEST, MS, CMODE0, CMODE1, DMODE
V
CC1
system pins : STB, /FRM, L1, L2, /DOUT, PULSE
Remark
/xxx indicates active low signals.