參數(shù)資料
型號: UPD16641N
廠商: NEC Corp.
英文描述: SOURCE DRIVER FOR 240-OUTPUT TFT-LCD 64 GRAY SCALES
中文描述: 240源驅(qū)動器輸出的TFT - LCD 64灰度
文件頁數(shù): 12/20頁
文件大?。?/td> 151K
代理商: UPD16641N
12
μ
PD16641
Switching Characteristics (T
A
= –10 to +75°C, V
DD1
= 3.0 to 3.6 V, V
DD2
= 3.0 to 3.6 V or 4.5 to 5.5 V, V
SS1
= V
SS2
= 0 V, t
r
= t
f
= 3.0 ns)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Start pulse delay time
t
PLH1
C
L
= 15 pF
2.0
17
ns
Start pulse delay time
t
PHL1
C
L
= 15 pF
2.0
17
ns
Driver output delay time 1
t
PLH21
6.0
12
μ
s
Driver output delay time 2
t
PLH31
V
O
: 0.1 V
3.2 V
8.0
14
μ
s
Driver output delay time 1
t
PHL21
6.0
10
μ
s
Driver output delay time 2
t
PHL31
V
DD2
= 3.3 V
2 k
+ 75 pF
×
2
V
O
: 3.2 V
0.1 V
8.0
12
μ
s
Driver output delay time 1
t
PLH22
6.0
10
μ
s
Driver output delay time 2
t
PLH32
V
O
: 0.1 V
4.9 V
8.0
12
μ
s
Driver output delay time 1
t
PHL22
6.0
8.0
μ
s
Driver output delay time 2
t
PHL32
V
DD2
= 5.0 V
2 k
+ 75 pF
×
2
V
O
: 4.9 V
0.1 V
8.0
10
μ
s
Input capacitance
C
I1
V
0
to V
10
, T
A
= 25°C
100
pF
Input capacitance
C
I2
STHR (L), T
A
= 25°C
10
15
pF
Input capacitance
C
I3
STHR (L), other than V
0
to V
10
T
A
= 25°C
7.0
10
pF
Timing Requirements (T
A
= –10 to +75°C, V
DD1
= 3.0 to 3.6 V, V
DD2
= 3.0 to 3.6 V or 4.5 to 5.5 V, V
SS1
= V
SS2
= 0 V,
t
r
= t
f
= 3.0 ns)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Clock pulse width
PW
CLK
22
ns
Clock low period
PW
CLK(L)
4.0
ns
Clock high period
PW
CLK(H)
4.0
ns
Data setup time
t
SETUP1
2.0
ns
Data hold time
t
HOLD1
2.0
ns
Start pulse setup time
t
SETUP2
2.0
ns
Start pulse hold time
t
HOLD2
2.0
ns
Start pulse low period
t
SPL
2
CLK
Start pulse rise time
t
SPR
80
CLK
STB setup time
t
SETUP3
1
CLK
Data invalid period
t
INV
1
CLK
Final data timing
t
LDT
1
CLK
CLK-STB time
t
CLK-STB
CLK
STB
or
7.0
ns
STB-CLK time
t
STB-CLK
STB
or
CLK
7.0
ns
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