參數(shù)資料
型號(hào)： UPD16641
廠商： NEC Corp.
英文描述： SOURCE DRIVER FOR 240-OUTPUT TFT-LCD 64 GRAY SCALES
中文描述： 240源驅(qū)動(dòng)器輸出的TFT - LCD 64灰度
文件頁(yè)數(shù)： 4/20頁(yè)
文件大?。?/td> 151K
代理商： UPD16641
4
μ
PD16641
3. PIN DESCRIPTION
Pin Symbol
Pin Name
Description
S
1
to S
240
Driver output
Output 64 gray scale analog voltages converted from digital signals.
D
00
to D
05
D
10
to D
15
D
20
to D
25
Display data input
Inputs 18-bit-wide display gray scale data (6 bits)
×
3 dots (RGB).
D
X0
: LSB, D
X5
: MSB
R/L
Shift direction select input
This pin inputs/outputs start pulses when two or more
μ
PD16641s are connected
in cascade. Shift direction of shift register is as follows:
R/L = H : STHR input, S
1
→
S
240
, STHL output
R/L = L : STHL input, S
240
→
S
1
, STHR output
STHR
Right shift start pulse I/O
R/L = H: Inputs start pulse.
R/L = L : Outputs start pulse.
STHL
Left shift start pulse I/O
R/L = H: Outputs start pulse.
R/L = L : Inputs start pulse.
V
sel
Driver voltage selection
Selects driver voltage. This pin is internally pulled up to V
DD2
.
V
sel
= V
DD2
or OPEN: V
DD2
= 3.3 V
±
0.3 V, V
sel
= L: V
DD2
= 5.0 V
±
0.5 V
CLK
Shift clock input
Inputs shift clock to shift register. Display data is loaded to data register at rising
edge of this pin.
Start pulse output goes high at rising edge of 80th clock after start pulse has been
input, and serves as start pulse to driver in next stage. 80th clock of driver in first
stage serves as start pulse of driver in next stage.
STB
Latch input
Contents of data register are latched at rising edge, transferred to D/A converter,
and output as analog voltage corresponding to display data. Contents of initial
shift register are cleared after STB has been input. One pulse of this signal is
input when
μ
PD16641 is started, and then device operates normally. For STB
input timing, refer to
Relations between STB, Start Pulse, and Blanking Period
in Switching Characteristic Waveform
.
V
0
to V
10
γ
-corrected power supply
Inputs
γ
-corrected power from external source.
V
SS2
≤
V
10
≤
V
9
≤
V
8
≤
V
7
≤
V
6
≤
V
5
≤
V
4
≤
V
3
≤
V
2
≤
V
1
≤
V
0
≤
V
DD2
V
SS2
≤
V
0
≤
V
1
≤
V
2
≤
V
3
≤
V
4
≤
V
5
≤
V
6
≤
V
7
≤
V
8
≤
V
9
≤
V
10
≤
V
DD2
Maintain gray scale power supply during gray scale voltage output.
V
DD1
Logic circuit power supply
3.3 V
±
0.3 V
V
DD2
Driver circuit power supply
V
sel
= V
DD2
or OPEN: V
DD2
= 3.3 V
±
0.3 V
V
sel
= L
: V
DD2
= 5.0 V
±
0.5 V
V
SS1
Logic ground
Ground
V
SS2
Driver ground
Ground
Caution Be sure to turn on power in the order V
DD1
, logic input, V
DD2
, and gray scale power (V
0
to V
10
), and
turn off power in the reverse order, to prevent the
μ
PD16641 from being damaged by latchup. Be
sure to observe this power sequence even during a transition period.
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PDF描述
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