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參數(shù)資料
| 型號(hào)： | UPD16640CN |
| 廠商： | NEC Corp. |
| 英文描述： | 300/309-OUTPUT TFT-LCD SOURCE DRIVER 64 GRAY SCALE |
| 中文描述： | 300/309-OUTPUT TFT - LCD的源驅(qū)動(dòng)64灰階 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 105K |
| 代理商： | UPD16640CN |
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Data Sheet S11269EJ1V1DS00
4
μ
PD16640C
3. PIN FUNCTIONS
Pin Symbol
Pin Name
Description
S
1
to S
309
Driver output
Output 64 gray scale analog voltages converted from digital signals.
O
sel
= H : 300 outputs (S
1
- S
150
, S
160
- S
309
)
O
sel
= L : 309 outputs (S
1
- S
309
)
Output pins S
151
to S
159
are invalid in 300-output mode.
Inputs 18-bit-wide display gray scale data (6 bits) x 3 dots (RGB).
D
X0
: LSB, D
X5
: MSB
D
00
to D
05
D
10
to D
15
D
20
to D
25
R,/L
Display data input
Shift direction select input
This pin inputs/outputs start pulses in cascade mode.
Shift direction of shift register is as follows:
R,/L = H : STHR input, S
1
→
S
309
, STHL output
R,/L = L : STHL input, S
309
→
S
1
, STHR output
R,/L = H : Inputs start pulse
R,/L = L : Outputs start pulse
R,/L = H : Outputs start pulse
R,/L = L : Inputs start pulse
Selects number of outputs. This pin is internally pulled up by V
DD1
power
supply.
O
sel
= H : 300 outputs
O
sel
= L : 309 outputs
Selects driver voltage. This pin is internally pulled up by V
DD2
power supply.
V
sel
= H : 300 outputs
V
sel
= L : 309 outputs
Inputs shift clock to shift register. Display data is loaded to data register at
rising edge of this pin.
When O
sel
= H, start pulse output goes high at rising edge of 100th clock after
start pulse has been input, and serves as start pulse to driver in next stage.
When O
sel
= L, start pulse output goes high at rising edge of 103rd clock after
start pulse has been input, and serves as start pulse to driver in next stage.
103rd clock of driver in first stage serves as start pulse of driver in next stage.
Contents of data register are latched at rising edge, transferred to D/A
converter, and output as analog voltage corresponding to display data.
Contents of internal shift register are cleared after STB has been input. One
pulse of this signal is input when
μ
PD16640C is started, and then device
operates normally. For STB input timing, refer to
8. SWITCHING
CHARACTERISTIC WAVEFORM.
Inputs
γ
-corrected power from external source.
V
SS2
+0.1 V
≤
V
10
≤
V
9
≤
V
8
≤
V
7
≤
V
6
≤
V
5
≤
V
4
≤
V
3
≤
V
2
≤
V
1
≤
V
0
≤
V
DD2
0.1 V
or
V
SS2
+0.1 V
≤
V
0
≤
V
1
≤
V
2
≤
V
3
≤
V
4
≤
V
5
≤
V
6
≤
V
7
≤
V
8
≤
V
9
≤
V
10
≤
V
DD2
0.1 V
Maintain gray scale power supply during gray scale voltage output.
Input data can be inverted when display data is loaded.
INV = H : Inverts and loads input data.
INV = L : Does not invert input data.
3.3 V
±
0.3 V
V
sel
= H : V
DD2
= 3.3 V
±
0.3 V
V
sel
= L : V
DD2
= 5.0 V
±
0.5 V
Ground
Ground
STHR
Right shift start pulse I/O
STHL
Left shift start pulse I/O
O
sel
Number of output selection
V
sel
Driver voltage selection
CLK
Shift clock input
STB
Latch input
V
0
to V
10
γ
-corrected power supply
INV
Data inversion input
V
DD1
V
DD2
Logic circuit power supply
Driver circuit power supply
V
SS1
V
SS2
Logic ground
Driver ground
Caution
Be sure to turn on power in the order V
DD1
, logic input, V
DD2
, and gray scale power (V
0
to V
10
),
and turn off power in the reverse order, to prevent the
μ
PD16640C from being damaged by latchup.
Be sure to observe this power sequence even during a transition period.
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