參數資料
型號: UPD16634AN
廠商: NEC Corp.
英文描述: 300-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 64 GRAY SCALE
中文描述: 300輸出的TFT - LCD源驅動程序完全兼容64灰階
文件頁數: 13/20頁
文件大?。?/td> 115K
代理商: UPD16634AN
Data Sheet S12595EJ2V0DS00
13
μ
PD16634A
Electrical Characteristics (T
A
= –10 to +75
°
C, V
DD1
= 3.3 V
±
0.3 V, V
DD2
= 8.0 V
±
0.5 V, V
SS1
= V
SS2
= 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Input leakage current
I
IL
±
1.0
μ
A
High-level output voltage
V
OH
STHR(STHL),I
O
=0 mA
V
DD1
0.1
V
Low-level output voltage
V
OL
STHR(STHL),I
O
=0 mA
0.1
V
γ
-corrected supply current
I
γ
V
0
V
9
= 8 V
V
0
,V
9
0.3
0.6
mA
Driver output current
I
VOH
V
X
=7 V, V
OUT
=1 V
Note1
0.5
mA
I
VOL
V
X
=1 V, V
OUT
=7 V
Note1
0.5
mA
Output voltage deviation
Note2
V
O
Input data : 00H to 3FH
±
5
±
20
mV
Average output voltage variation
Note3
V
AV
Input data : 00H to 3FH
±
10
mV
Output voltage range
V
O
Input data : 00H to 3FH
0.1
V
DD2
0.1
V
Logic part dynamic current
consumption
Notes4,5
I
DD1
V
DD1,
when with no load
0.5
3.5
mA
Driver part dynamic current
consumption
Notes4,5
I
DD2
V
DD2,
when with no load
2.2
8.0
mA
Notes 1.
V
X
refers to the output voltage of analog output pins S
1
to
S
300
.
V
OUT
refers to the voltage applied to analog output pins S
1
to S
300
.
2.
The output voltage deviation refers to the voltage difference between adjoining output pins when the
display data is the same (within the chip).
3.
The average output voltage variation refers to the average output voltage difference between chips. The
average output voltage refers to the average voltage between chips when the display data is the same.
4.
The STB cycle is defined to be 20
μ
s at f
CLK
= 40 MHz. The TYP. values refer to an all black or all white
input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern.
5.
Refers to the current consumption per driver when cascades are connected under the assumption of
SVGA single-sided mounting (10 units).
Switching Characteristics (T
A
=
10 to +75
°
C, V
DD1
= 3.3 V
±
0.3 V, V
DD2
= 8.0 V
±
0.5 V, V
SS1
= V
SS2
= 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Start pulse delay time
t
PLH1
C
L
= 25 pF
13
20
ns
Driver output delay time
t
PHL2
C
L
= 125 pF, R
L
= 4 k
Note
3.7
8
μ
s
t
PHL3
5.3
14
μ
s
t
PLH2
3.0
8
μ
s
t
PLH3
5.3
14
μ
s
Input capacitance
C
1
STHR,STHL excluded, T
A
= 25
°
C
5.4
15
pF
C
2
7.6
15
pF
Note
Load condition
output
C
L
C
L
C
L
R
L
R
L
R
L
R
L
= 1k
C
L
= 25pF
C
L
R
L
C
L
#
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