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參數(shù)資料
| 型號： | UPD16448AN |
| 廠商： | NEC Corp. |
| 英文描述： | SOURCE DRIVER FOR 240-OUTPUT TFT-LCD NAVIGATION, AUTOMOBILE LCD-TV |
| 中文描述： | 240源驅(qū)動器輸出的TFT - LCD導(dǎo)航，汽車液晶電視 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大小： | 133K |
| 代理商： | UPD16448AN |
16
μ
PD16448A
[Cautions on Use]
1.
Turn ON power to V
DD1
, logic input, V
DD2
, and video signal input in that order to prevent
destruction due to latchup, and turn off power in the reverse sequence. Observe this power
sequence even during the transition period.
This IC is designed to input successive signals such as chrome signals. The input band of the
video signals is designed to be 9 MHz
MAX
. If video signals faster than that are input, display is
not performed correctly.
Insert a bypass capacitor of 0.1
μ
F between V
DD1
and V
SS1
and between V
DD2
and V
SS2
. If the
power supply is not reinforced, the sampling voltage may be abnormal if the supply voltage
fluctuates.
Display may not be correctly performed if noise is superimposed on the start pulse pin.
Therefore, be sure to input a reset signal during the vertical blanking period.
Even if the start pulse width is extended by half a clock or more, sampling start timing SHP
1
is
not affected, and the sampling operation is performed normally.
When the multiplexer circuit is used in the vertical stripe mode, C
1
, C
2
, and C
3
are
simultaneously sampled at the rising edge of SHP
n
. Internally, however, only CLI
1
is valid.
Therefore, input a shift clock to CLI
1
only. At this time, keep the CLI
2
and CLI
3
pins to "L".
When using the multiplexer circuit in the delta array mode or mosaic array mode, C
1
, C
2
, and C
3
are sequentially sampled. Input a three-phase clock to CLI
1
through CLI
3
. (For the sampling
timing, refer to 2. FUNCTION DESCRIPTION.)
The recommended timing of t
R-1
and PW
RES
on starting is shown below. (The following timing
chart shows simultaneous sampling.)
An INH pulse width of at least 5 clocks is required to reset the internal logic. Unless the INH
pulse is input after reset, sampling is not performed in the correct sequence.
2.
3.
4.
5.
6.
7.
CLI
1
RESET
INH
STHR (STHL)
SHP
1 to 3
SHP
4 to 6
SHP
7 to 9
1
2
3
4
5
1
2
3
PW
RES
t
ISETUP
t
IHOLD
t
R–I
PW
INH
: 5 clocks
MIN.
3 clocks
MIN.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD16449 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UPD16449 Data Sheet | Data Sheet[05/2002] |
| UPD16449N | 制造商:NEC 制造商全稱:NEC 功能描述:SOURCE DRIVER FOR 240-OUTPUT TFT-LCD |
| UPD16449N-XXX | 制造商:NEC 制造商全稱:NEC 功能描述:SOURCE DRIVER FOR 240-OUTPUT TFT-LCD |
| UPD16449P | 制造商:NEC 制造商全稱:NEC 功能描述:SOURCE DRIVER FOR 240-OUTPUT TFT-LCD |
| UPD16454A | 制造商:NEC 制造商全稱:NEC 功能描述:MOS INTEGRATED CIRCUIT |
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