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參數(shù)資料
| 型號(hào)： | UPD16340 |
| 廠商： | NEC Corp. |
| 英文描述： | 96-BIT AC-PDP DRIVER |
| 中文描述： | 96位交流PDP驅(qū)動(dòng) |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大小： | 97K |
| 代理商： | UPD16340 |
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Data Sheet S13685EJ1V0DS00
4
μ
PD16340
PIN FUNCTIONS
Symbol
Pin Name
Description
/LBLK
Low blanking input
/LBLK
=
L : All output
=
L
/HBLK
High blanking input
/HBLK
=
L : All output
=
H
/LE
Latch enable input
Latch on a falling edge
HZ
Output high impedance
H: All output set to the high-impedance state
/CLR
Register clear input
L: All shift register data cleared to the L level
A
1
-A
3(6)
RIGHT data input/output
Note
R,/L
=
H, the parenthesized pins are used in 6-bit input mode.
A
1
-A
3(6)
: Input, B
1
-B
3(6)
: Output
B
1
-B
3(6)
LEFT data input/output
Note
R,/L
=
L, the parenthesized pins are used in 6-bit input mode.
A
1
-A
3(6)
: Output, B
1
-B
3(6)
: Input
CLK
Clock input
Shift on a rising edge
R,/L
Shift control input
H: Right shift mode
SR
1
: A
1
→
S
1
.......S
94
→
B
1
(SR
2
and SR
3
also shift in the same direction.)
Left shift mode
SR
1
: B
1
→
S
94
.......S
1
→
A
1
(SR
2
and SR
6
also shift in the same direction.)
IBS
Input mode switch
H: 32-bit shift registers, 3-bit input mode
L: 16-bit shift registers, 6-bit input mode
O
1
to O
96
High withstand voltage output
80 V, +50/–75 mA MAX.
V
DD1
Logic power supply
5 V
±
10 %
V
DD2
Driver power supply
10 to 70 V
V
SS1
Logic ground
Connect to system ground
V
SS2
Driver ground
Connect to system ground
Note
In 3-bit input mode, unused I/O pins must be held at the L level.
To use for module, the back side of IC chip must be held at the V
SS
(GND) level.
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