
11
μ
PC659A
ATTENTION FOR APPLICATION
Converted data output
Analog signal is captured at the rising edge, and converted data will be output at the rising edge after 1 clock pulse.
For the
μ
PC659, 2 clock pulses.
Analog input terminal
In case the pedestal level is clamped, the clamp circuit uses the soft clamp circuit to protect the burst level. However,
if a high impedance output is connected to the V
IN
pin (pin 4), the burst level will be reduced (for example, for an
external impedance of 10
, the burst level is reduced by approx. 3 %).
Therefore, connect the lowest possible impedance signal to the analog signal input pin.
Clamp pulse
Low output
impedance
buffer
P
CL
Clamp voltage
V
CL
AGND
PC659A
μ
V
IN
4
6
7
If don’s use the clamp circuit
P
CL
pin (pin 6) and GND must be short-circuit. And insert by-pass capacitor of about 0.1
μ
F between the V
CL
pin
(pin 7) and GND. Input analog signal to V
IN
pin (pin 4).
In case an external clamp circuit is used, connect the P
CL
pin (pin 6) to GND, and leave the V
CL
pin (pin 7)
unconnected. Set the voltage of the V
IN
pin (pin 4) between 2.3 V and 3.3 V.
Clamp voltage
There is a few difference clamp voltage between the supply clamp voltage V
CL
(pin 7) and really clamp voltage.
Really clamp voltage = V
CL
+
α
Take account of the
α
(about
±
20 mV) at supply V
CL
to pin 7.
When reference voltage is set from external, V
RB
(pin 10) = 2.3 V, V
RT
(pin 1) = 3.3 V .
Circuit current
TYP. (Unit: mA)
Analog circuit current
37
Digital circuit current
6
Sum
43
Set the sampling clock frequency between 1 MHz and 20 MHz. If a frequency outside this range is used, the internal
sample-and-hold circuit will not function properly.
First apply 5 V to the AV
CC
pins (pins 3 and 11) and the DV
CC
pin (pin 18), then input the analog signal to the V
IN
pin (pin 4). If the analog signal is input first, the output data may latch up.