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參數(shù)資料
| 型號： | UPC1935GR |
| 廠商： | NEC Corp. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | DC-DC CONVERTER CONTROL IC |
| 中文描述： | 的DC - DC轉(zhuǎn)換器控制IC |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 185K |
| 代理商： | UPC1935GR |
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Data Sheet G13418EJ3V0DS00
13
μ
PC1935
2.6
Timer Latch-Method Short Circuit Protection Circuit
When the outputs of the converters for each channel drop, the FB outputs of the error amplifiers of those outputs go
high (FB
3
output goes low). If the FB output exceeds the timer latch input detection voltage (V
TH
= 1.9 V) (FB
3
output goes
lower than the timer latch input detection voltage (V
TH
= 0.63 V)), then the output of the SCP comparator goes low, and Q
1
goes off.
When Q
1
turns OFF, the constant-current supply charges C
DLY
via the DLY pin. The DLY pin is internally connected to a
flip-flop. When the DLY pin voltage reaches the UV detection voltage (V
UV
= 0.8 V (TYP)), the output Q of the flip-flop goes
low, and the output stage of each channel is latched to OFF (refer to
Figure 2-1 Block Diagram
).
The logic of channels 1 and 2 is reverse to that of channel 3. Consequently, an inverter circuit is inserted between the
FB output of channels 1 and 2, and SCP comparator input.
Make the power supply voltage briefly less than the reset voltage (V
CCR
, 1.0 V TYP) to reset the latch circuit when the
short-circuit protection circuit has operated.
2.7
Output Circuit
The output circuit has an N-channel open-drain output providing an output withstand voltage of 30 V (absolute maximum
rating), and an output current of 21 mA (absolute maximum rating).
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