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參數(shù)資料
| 型號： | UPC1935 |
| 廠商： | NEC Corp. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | DC-DC CONVERTER CONTROL IC |
| 中文描述： | 的DC - DC轉換器控制IC |
| 文件頁數(shù)： | 18/28頁 |
| 文件大?。?/td> | 185K |
| 代理商： | UPC1935 |
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Data Sheet G13418EJ3V0DS00
18
μ
PC1935
3.5.2
Channel 2 (for step-up)
The ON/OFF signal control method of the output oscillation of channel 2 is to input the ON/OFF signal from ON
2
as
shown in Figure 3-4. The PWM converter can be turned ON/OFF by controlling the level of the DTC
2
pin. However, it is
necessary to keep the level of the FB
2
output low (the SCP comparator input high) so that the timer latch does not start
when the PWM converter is OFF. In this circuit example, the FB
2
output level is controlled by controlling the level of the I
I2
pin.
Figure 3-4 ON/OFF Control (channel 2: step-up)
(1) When ON
2
is high: OFF status
Q
21
: ON
→
DTC
2
pin: Low level
→
Output duty of PWM comparator: 0 %
D
21
: ON
→
I
I2
pin: High level
→
FB
2
output: Low level
→
SCP comparator output: High level
→
Timer latch stops.
(2) When ON
2
is low: ON status
Q
21
: OFF
→
C
21
is charged in the sequence of [V
REF
→
R
23
→
C
21
]
→
DTC
2
pin voltage rises
→
Soft start
D
21
: OFF
→
I
I2
pin: Low level
→
FB
2
output: High level
→
SCP comparator output: Low level
→
Q
1
is OFF
→
Charging C
DLY
starts (timer latch start).
Caution Keep the low-level voltage of the DTC
2
pin within 1.2 V and the high-level voltage of the I
I2
pin at
0.3 V or higher. The maximum voltage that is applied to the I
I2
pin must be equal to or lower than
V
REF
.
+
+
–
+
–
–
+
V
O2
D
21
ON
2
Q
21
Q
1
PWM comparator
SCP comparator
(common to each channel)
C
21
DTC
2
R
22
V
REF
C
DLY
FB
2
DLY
R
21
R
24
R
23
I
I2
0.3 V
0.63 V
Error
amplifier
To output stage
Oscillation section
(common to each channel)
(Converter
output
voltage)
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