參數(shù)資料
型號(hào): UPC1251GR-9LG-E2-A
廠商: NEC Corp.
英文描述: BIPOLAR ANALOG INTEGRATED CIRCUIT SINGLE POWER SUPPLY DUAL OPERATIONAL AMPLIFIERS
中文描述: 雙極模擬集成電路單電源雙運(yùn)算放大器
文件頁數(shù): 4/12頁
文件大?。?/td> 229K
代理商: UPC1251GR-9LG-E2-A
Data Sheet G17929EJ3V0DS
4
μ
PC1251GR-9LG,
μ
PC1251MP-KAA,
μ
PC358GR-9LG
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
V
±
V
+
MIN.
TYP.
MAX.
Unit
Power Supply Voltage (Split)
Power Supply Voltage (V
±
1.5
±
15
V
= GND)
+
3
+
30
V
ELECTRICAL CHARACTERISTICS
μ
PC1251GR-9LG,
μ
PC1251MP-KAA,
μ
PC358GR-9LG (T
A
= 25
°
C, V
+
=
+
5 V, V
= GND)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input Offset Voltage
V
IO
R
S
= 0
Ω
±
2
±
5
±
7
mV
Input Offset Current
Input Bias Current
Note1
I
IO
±
50
nA
I
B
14
250
nA
Large Signal Voltage Gain
Circuit Current
Note2
A
V
R
L
2 k
Ω
25000
100000
I
CC
R
L
=
, I
O
= 0 A
0.7
1.2
mA
Common Mode Rejection Ratio
CMR
65
70
dB
Supply Voltage Rejection Ratio
SVR
65
100
dB
Output Voltage Swing
V
O
R
L
= 2 k
Ω
(Connect to GND)
0
V
+
1.5
V
+
1.5
V
Common Mode lnput Voltage Range
V
ICM
0
V
Output Source Current
I
O SOURCE
V
IN (
+
)
=
+
1 V, V
IN (
)
= 0 V
20
40
mA
Output Sink Current
I
O SINK1
V
IN (
)
=
+
1 V, V
IN (
+
)
= 0 V
10
20
mA
I
O SINK2
V
IN (
)
=
+
1 V, V
IN (
+
)
= 0 V, V
O
= 200 mV
12
50
μ
A
Channel Separation
f = 1 to 20 kHz
120
dB
μ
PC1251GR(5)-9LG,
μ
PC1251MP(5)-KAA,
μ
PC358GR(5)-9LG (T
A
= 25
°
C, V
+
=
+
5 V, V
= GND)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input Offset Voltage
V
IO
R
S
= 0
Ω
±
2
±
5
±
3
mV
Input Offset Current
Input Bias Current
Note1
I
IO
±
50
nA
I
B
14
60
nA
Large Signal Voltage Gain
Circuit Current
Note2
A
V
R
L
2 k
Ω
50000
100000
I
CC
R
L
=
, I
O
= 0 A
0.7
0.9
mA
Common Mode Rejection Ratio
CMR
65
70
dB
Supply Voltage Rejection Ratio
SVR
65
100
dB
Output Voltage Swing
V
O
R
L
= 2 k
Ω
(Connect to GND)
0
V
+
1.5
V
+
1.4
V
Common Mode lnput Voltage Range
V
ICM
0
V
Output Source Current
I
O SOURCE
V
IN (
+
)
=
+
1 V, V
IN (
)
= 0 V
30
40
mA
Output Sink Current
I
O SINK1
V
IN (
)
=
+
1 V, V
IN (
+
)
= 0 V
15
20
mA
I
O SINK2
V
IN (
)
=
+
1 V, V
IN (
+
)
= 0 V, V
O
= 200 mV
30
50
70
μ
A
Channel Separation
f = 1 to 20 kHz
120
dB
Notes1.
The input bias current flows in the direction where the IC flows out because the first stage is configured with a
PNP transistor.
2.
This is a current that flows in the internal circuit. This current will flow irrespective of the channel used.
<R>
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