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參數(shù)資料
| 型號(hào)： | UPB1505GR-E1 |
| 元件分類： | 諧振器 |
| 英文描述： | PRESCALER, PDSO8 |
| 封裝： | 0.225 INCH, PLASTIC, SOP-8 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 60K |
| 代理商： | UPB1505GR-E1 |
2
PB1505GR
Data Sheet P10872EJ3V0DS00
PIN NO.
SYMBOL
ASSIGNMENT
FUNCTIONS AND EXPLANATION
Input frequency from an external VCO output.
Must be coupled with capacitor (e.g. 1 000 pF) for DC cut.
Supply voltage 5.0
±0.5 V for operation. Must be connected bypass capacitor
(e.g. 1 000 pF) to minimize ground impedance.
Divided ratio control can be governed by following input data to these pins.
This frequency output can be interfaced to CMOS PLL.
Must be coupled with capacitor (e.g. 1 000 pF) for DC cut.
This pin must be connected to the system ground with minimum inductance.
Ground pattern on the board should be formed as wide as possible.
(Track length should be kept as short as possible.)
This pin must be connected bypass capacitor (e.g. 1 000 pF) to minimize ground
impedance.
1
IN
Frequency input
pin
2VCC
Power supply pin
3
SW1
Divided ratio
control input pin 1
6
SW2
Divided ratio
control input pin 2
4
OUT
Divided frequency
output pin
5
GND
Ground pin
7
8
IN
Frequency-input
bypass pin
SELECTOR GUIDE
FEATURES
PRODUCT
ICC
fin
VCC
PACKAGE
PIN ASSIGNMENT
NUMBER
(mA)
(GHz)
(V)
2.5 GHz /
÷512, ÷256
PB586G
28
0.5 to 2.5
5
8 pin SOP
2.5 GHz /
÷128, ÷64
PB588G
26
0.5 to 2.5
5
8 pin SOP
3.0 GHz /
÷256, ÷128, ÷64
PB1505GR
14
0.5 to 3.0
5
8 pin SOP
Typical of prescaler
NEC original
INTERNAL BLOCK DIAGRAM
1 / 64
1 / 2
Buff.
1
8
36
5, 7
GND
SW1
SW2
INPUT
BYPASS
2
VCC
4
OUTPUT
Notice Typical performance. Please refer to Electrical Characteristics in detail.
To know the associated products, please refer to their latest data sheets.
PIN DESCRIPTIONS
H
L
SW2
SW1
1/64
1/128
HL
1/256
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