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| 型號： | UP-S6-SP605-CONN-G |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL SPARTAN 6 SP605 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Spartan®-6 |
| 附件類型： | 升級套件 |
| 適用于相關(guān)產(chǎn)品： | Spartan? FPGA 評估套件 |
| 配用： | 122-1604-ND - KIT EVAL SPARTAN 6 SP605 122-1605-ND - KIT EVAL SPARTAN 6 SP605 |
Spartan-6 Family Overview
DS160 (v2.0) October 25, 2011
Product Specification
2
Spartan-6 FPGA Feature Summary
Table 1: Spartan-6 FPGA Feature Summary by Device
Device
Logic
Cells(1)
Configurable Logic Blocks (CLBs)
DSP48A1
Slices(3)
Block RAM Blocks
CMTs(5)
Memory
Controller
Blocks
(Max)(6)
Endpoint
Blocks for
PCI Express
Maximum
GTP
Transceivers
Total
I/O
Banks
Max
User
I/O
Slices(2)
Flip-Flops
Max
Distributed
RAM (Kb)
18 Kb(4)
Max (Kb)
XC6SLX4
3,840
600
4,800
75
8
12
216
2
0
4
132
XC6SLX9
9,152
1,430
11,440
90
16
32
576
2
0
4
200
XC6SLX16
14,579
2,278
18,224
136
32
576
2
0
4
232
XC6SLX25
24,051
3,758
30,064
229
38
52
936
2
0
4
266
XC6SLX45
43,661
6,822
54,576
401
58
116
2,088
4
2
0
4
358
XC6SLX75
74,637
11,662
93,296
692
132
172
3,096
6
4
0
6
408
XC6SLX100
101,261
15,822
126,576
976
180
268
4,824
6
4
0
6
480
XC6SLX150
147,443
23,038
184,304
1,355
180
268
4,824
6
4
0
6
576
XC6SLX25T
24,051
3,758
30,064
229
38
52
936
2
1
2
4
250
XC6SLX45T
43,661
6,822
54,576
401
58
116
2,088
4
2
1
4
296
XC6SLX75T
74,637
11,662
93,296
692
132
172
3,096
6
4
1
8
6
348
XC6SLX100T
101,261
15,822
126,576
976
180
268
4,824
6
4
1
8
6
498
XC6SLX150T
147,443
23,038
184,304
1,355
180
268
4,824
6
4
1
8
6
540
Notes:
1.
Spartan-6 FPGA logic cell ratings reflect the increased logic cell capability offered by the new 6-input LUT architecture.
2.
Each Spartan-6 FPGA slice contains four LUTs and eight flip-flops.
3.
Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an accumulator.
4.
Block RAMs are fundamentally 18 Kb in size. Each block can also be used as two independent 9 Kb blocks.
5.
Each CMT contains two DCMs and one PLL.
6.
Memory Controller Blocks are not supported in the -3N speed grade.
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