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參數(shù)資料
| 型號： | UCC5950D |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | POWER FACTOR CORRECTOR |
| 中文描述： | 10位數(shù)字到模擬轉換器 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 228K |
| 代理商： | UCC5950D |
ABSOLUTE MAXIMUM RATINGS
VDD Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Input Voltage, Any Input. . . . . . . . . . . . . . . . –0.3V to VDD+0.3V
Output Current, Any Output . . . . . . . . . . . . . . . . . . . . . . . .
±
5mA
Operating Temperature . . . . . . . . . . . . . . . . . .
55
°
C to +150
°
C
Storage Temperature . . . . . . . . . . . . . . . . . . . .
65°
C to +150
°
C
Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
°
C
All voltages with respect to GND. All currents are positive into,
negative out of, the specified terminal. Consult Packaging Sec-
tion of Databook for thermal limitations and considerations of
packages.
CONNECTION DIAGRAM
DIL-8, SOIC-8 (Top View)
N or J, D Package
UCC5950
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, all specifications apply for 4.5V < VDD < 5.5V, REFOUT
Load < 100pF, DACOUT Load < 100pF, 0
°
C < T
A
< +70
°
C, and T
A
= T
J
.
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNITS
OVERALL SECTION
Supply Current
Supply Current
REFERENCE SECTION
REFOUT Output Voltage
REFOUT Change with VDD
REFOUT Change with Load
D/A SECTION
Integral Nonlinearity
Differential Nonlinearity
Full Scale Difference from 1.4924 x REF
Zero Scale Difference from 0.5089 x REF
DACOUT Full Scale Rise/Fall Time
DACOUT Full Scale Settling Time (TS)
DACOUT Change with VDD
DACOUT Change with Load
LOGIC SECTION
Logic Input Threshold
Logic Input Current
Logic Input Capacitance
SLOD Setup Time to SCLK low (TSLS)
SLOD Hold Time from SCLK high (TSLH)
SDIO Setup Time to SCLK high (TDS)
SDIO Hold Time from SCLK high (TDH)
SLEEP = 0V
SLEEP = 5V
1.5
0.1
5
10
mA
μ
A
2.10
2.15
1
1
2.20
10
10
V
4.5V < VDD < 5.5V
–1mA < I
REFOUT
< 1mA
mV
mV
(Note 1)
2
1
8
8
LSB
LSB
LSB
LSB
μ
s
μ
s
mV
mV
–8
–8
From 10% to 90% of swing (Note 4)
(Note 2, 3, 4)
4.5V < VDD < 5.5V
–1mA < I
DACOUT
< 1mA
0.7
1.4
1.5
1.2
1.1
2.5
10
10
1.5
2.5
3.5
5
10
V
μ
A
pF
ns
ns
ns
ns
0V < V
IN
< VDD
(Note 4)
(Note 4)
From 10
TH
SCLK high (Note 4)
(Note 4)
(Note 4)
2.7
50
50
15
7
Note 1: Integral nonlinearity is defined as the worst deviation of the converter output from the best-fit straight line through
all converter output codes.
Note 2: From 10
TH
Rising Edge of SCLK.
Note 3: Settling time is to 1% of final value.
Note 4: Guaranteed by design. Not 100% tested in production.
2
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