參數(shù)資料
型號: UCB1400
廠商: NXP Semiconductors N.V.
元件分類: Codec
英文描述: Audio codec with touch screen controller and power management monitor
中文描述: 音頻編解碼器與觸摸屏控制器和電源管理監(jiān)控
文件頁數(shù): 38/63頁
文件大?。?/td> 674K
代理商: UCB1400
Philips Semiconductors
UCB1400
Audio codec with touch screen controller
and power management monitor
Product data
Rev. 02 — 21 June 2002
38 of 63
9397 750 09611
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
12.7 Power-down Control/Status register (index 0x26)
This read/write register is used to program power-down states and monitor
subsystem readiness. The lower half of this register is read only status, a ‘1’
indicating that the subsection is ‘ready’. ‘Ready’ is defined as the subsection able to
perform in its nominal state. When this register is written, the bit values that come in
on AC-link will have no effect on read-only bits 0 - 7.
When the ‘Codec Ready’ indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that
the UCB1400 control and status registers are in a fully operational state. The AC ’97
Controller must further probe this Power-down Control/Status register to determine
exactly which subsections, if any, are ready.
Table 23:
Register address: 0x26; default: 000X
Bit
D15
Symbol
X
Bit
D7
Symbol
X
Power-down Control/Status register
D14
X
D6
X
D13
PR5
D5
X
D12
PR4
D4
X
D11
PR3
D3
REF
D10
X
D2
X
D9
PR1
D1
DAC
D8
PR0
D0
ADC
Table 24:
Bit
D15 - D14
D13
D12
Description of Power-down Control/Status register bits
Symbol
Type
X
R
PR5
RW
PR4
RW
Description
Reserved.
Internal clock disable.
Digital interface (AC-link) power-down (external
clock off).
Audio V
REF
power-down.
Reserved.
Audio DAC and output path power-down.
Audio ADC and input path power-down.
Reserved.
Audio V
REF
up to nominal level.
Reserved.
Audio DAC section ready to accept data.
Audio ADC section ready to transmit data.
D11
D10
D9
D8
D7 - D4
D3
D2
D1
D0
PR3
X
PR1
PR0
X
REF
X
DAC
ADC
RW
R
RW
RW
R
R
R
R
R
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