參數(shù)資料
型號(hào): UCB1100
廠商: NXP Semiconductors N.V.
英文描述: Advanced modem/audio analog front-end
中文描述: 先進(jìn)的調(diào)制解調(diào)器/音頻模擬前端
文件頁(yè)數(shù): 30/36頁(yè)
文件大?。?/td> 290K
代理商: UCB1100
Philips Semiconductors
Preliminary specification
UCB1100
Advanced modem/audio analog front-end
1998 May 08
30
8.0
CONTROL REGISTER OVERVIEW
Address 0:
IO port data register
BIT
MODE
SYMBOL
REMARK
RESET
9:0
R/W
io_data[9:0]
The bits in the write register provide the data of the io pin when programmed as output.
The bits in the read register return the actual state of the associated io pin.
0
Address 1:
IO port direction register
BIT
MODE
SYMBOL
REMARK
RESET
9:0
R/W
io_dir[9:0]
If ‘1’, the associated io pin is defined as output.
If ‘0’, the associated io pin is defined as input
0
15
R/W
sib_zero
If ‘1’, the sibdout pin is forced ‘0’ during the second sib word.
If ‘0’, the sibdout pin tristated during the second sib word
0
Address 2:
Rising edge interrupt enable register
BIT
MODE
SYMBOL
REMARK
RESET
9:0
R/W
io_ris_int[9:0]
If ‘1’, the rising edge interrupt of the associated io pin is enabled
0
11
R/W
adc_ris_int
If ‘1’, the rising edge interrupt of the adc_ready signal is enabled
0
12
R/W
tspx_ris_int
If ‘1’, the rising edge interrupt of the tspx signal is enabled
0
13
R/W
tsmx_ris_int
If ‘1’, the rising edge interrupt of the tsmx signal is enabled
0
14
R/W
tclip_ris_int
If ‘1’, the rising edge interrupt of the telecom clip is enabled
0
15
R/W
aclip_ris_int
If ‘1’, the rising edge interrupt of the audio clip is enabled
0
Address 3:
Falling edge interrupt enable register
BIT
MODE
SYMBOL
REMARK
RESET
9:0
R/W
io_fal_int[9:0]
If ‘1’, the falling edge interrupt of the associated io pin is enabled
0
11
R/W
adc_fal_int
If ‘1’, the falling edge interrupt of the adc_ready signal is enabled
0
12
R/W
tspx_fal_int
If ‘1’, the falling edge interrupt of the tspx signal is enabled
0
13
R/W
tsmx_fal_int
If ‘1’, the falling edge interrupt of the tsmx signal is enabled
0
14
R/W
tclip_fal_int
If ‘1’, the falling edge interrupt of the telecom clip is enabled
0
15
R/W
aclip_fal_int
If ‘1’, the falling edge interrupt of the audio clip is enabled
0
Address 4:
Interrupt clear/status register
BIT
MODE
SYMBOL
REMARK
RESET
9:0
W
io_int_clr[0:9]
A ‘0’ to ‘1’ transition clears the interrupt of the associate io pin
0
R
io_int_stat[9:0]
Returns the actual interrupt status of the associated io pin
11
W
adc_int_clr
A ‘0’ to ‘1’ transition clears the interrupt adc_ready signal
0
R
adc_int_stat
Returns the actual interrupt status of the adc_ready signal
12
W
tspx_int_clr
A ‘0’ to ‘1’ transition clears the interrupt of the tspx signal
0
R
tspx_int_stat
Returns the actual interrupt status of the tspx signal
13
W
tsmx_int_clr
A ‘0’ to ‘1’ transition clears the interrupt of the tsmx signal
0
R
tsmx_int_stat
Returns the actual interrupt status of the tsmx signal
14
W
tclip_int_clr
A ‘0’ to ‘1’ transition clears the interrupt of the telecom clip
0
R
tclip_int_stat
Returns the actual interrupt status of the telecom clip
15
W
aclip_int_clr
A ‘0’ to ‘1’ transition clears the interrupt of the audio clip
0
R
aclip_int_stat
Returns the actual interrupt status of the audio clip
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