參數(shù)資料
型號(hào): UC5613PWPTR
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: 1.5 A, Very low drop voltage regulators
中文描述: 終結(jié)者
文件頁(yè)數(shù): 1/5頁(yè)
文件大?。?/td> 301K
代理商: UC5613PWPTR
Complies with SCSI, SCSI-2
and SPI-2 Standards
5pF Channel Capacitance
during Disconnect
Meets SCSI Hot Plugging
400mA Sourcing Current for
Termination
+100mA Sinking Current for
Active Negation
1V Dropout Voltage Regulator
Logic High Command
Disconnects all Termination
Lines
100
μ
A Supply Current in
Disconnect Mode
Trimmed Termination Current
to 5%
Trimmed Impedance to 5%
Low Thermal Resistance
Surface Mount Packages
The UC5612 provides 9 lines of active termination for a SCSI (Small Computer
Systems Interface) parallel bus. The SCSI standard recommends active termi-
nation at both ends of the cable segment.
The only functional differences between the UC5603 and UC5612 is the ab-
sence of the negative clamps on the output lines. Parametrically, the UC5612
has a 5% tolerance on impedance and current compared to a 3% tolerance on
the UC5603. Custom power packages are utilized to allow normal operation at
full power (2 Watts).
The UC5612 provides a disconnect feature which, when opened or driven high,
disconnects all terminating resistors, disables the regulator and greatly reduces
standby power consumption. The output channels remain high impedance even
without Termpwr applied. A low channel capacitance of 5pF allows interim
points of the bus to have little to no effect on the signal integrity.
Internal circuit trimming is utilized, first to trim the impedance to a 5% tolerance,
and then most importantly, to trim the output current to a 5% tolerance, as close
to the maximum SCSI specification as possible. This maximizes the noise mar-
gin in fast SCSI operation. Other features include thermal shutdown and cur-
rent limit.
This device is offered in low thermal resistance versions of the industry stand-
ard 16 pin narrow body SOIC, 16 pin ZIP (zig-zag in line package) and 24 pin
TSSOP.
UC5612
9-Line Low Capacitance SCSI Active Terminator
FEATURES
DESCRIPTION
BLOCK DIAGRAM
Circuit Design Patented
3/97
UDG-94133
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