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參數(shù)資料
| 型號： | UART_AU1000_REV002 |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-bit MCU for automotive with 16 to 60 Kbyte Flash, ADC, CSS, 5 timers, SPI, SCI, I2C interface |
| 中文描述： | 編寫具有了AMD Alchemy的UART設(shè)備驅(qū)動程序？解決方案Au1000？處理器？ |
| 文件頁數(shù)： | 4/4頁 |
| 文件大?。?/td> | 32K |
| 代理商： | UART_AU1000_REV002 |
4
Application Note
Rev. 002
September 2001
Writing a UART Device Driver for the Au1000 Processor
The NS16550 baud rate clock divisor registers DLL/DLM are consolidated into a single
uart_clkdiv register on the Au1000.
The LCR[DLAB] bit is not implemented (since it is not needed).
The MCR[AFE] bit is not implemented.
Programming Considerations
The operation of the Au1000 processor UART is very similar to that of the NS16550. The differences
are outlined below.
Before the UART can be used, it must be enabled via the uart_enable register.
All register accesses must be 32-bits. Byte-wide accesses to the UART registers do not work.
Furthermore, 32-bit register accesses works for both endian modes without the need for byte
swapping.
The Au1000 UART baud rate clock is derived from the Au1000 processor PBUS frequency, not
the personal computer industry standard 1.3xxMHz frequency used for the NS16550. The baud
rate divider programmed into uart_clkdiv must be computed relative to the PBUS frequency of
your system.
Only UART4 has the modem control signals available.
As with all peripherals integrated into the Au1000 processor, all register accesses should be through
the KSEG1 region. This region is un-mapped, and more importantly, non-cached. All non-cached
accesses proceed through the write buffer, WB, where write-merging takes place. (Please see Au1000
Processor Data Book[2].) Write buffer write-merging combines successive writes to the same address
into a single write. For peripheral register accesses, this is incorrect. For example, if two bytes are
written to uart_txdata, only the second byte survives the write-merging stage, so the first byte is lost.
As a result, accesses to the UART registers must flush the write buffer (before and/or) after a register
write. Flushing the write buffer also guarantees that previous writes have been posted to the
peripheral (as opposed to sitting indefinitely in the write buffer until a write buffer flush event
occurs). The write buffer is flushed with a SYNC instruction rather than a non-cached read (since a
read of a peripheral register can have unintended side-effects).
References:
[1] National Semiconductor, NS16550 Data Sheet. http://www.national.com/pf/PC/PC16550D.html
[2] Au1000 Processor Data Book.
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