參數(shù)資料
型號: UAA3522
廠商: NXP Semiconductors N.V.
英文描述: Low power dual-band GSM transceiver with an image rejecting front-end
中文描述: 低功耗雙頻拒絕與前面的形象GSM收發(fā)端
文件頁數(shù): 21/28頁
文件大小: 148K
代理商: UAA3522
2000 Feb 18
21
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
SERIAL TIMING CHARACTERISTICS
General conditions: V
CC
= 2.8 V; T
amb
= 25
°
C; see Fig.6; unless otherwise specified.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Serial programming clock (pin CLK)
t
r
t
f
T
cy(clk)
Enable programming (pin EN)
rise time
fall time
clock cycle time
100
10
10
40
40
ns
ns
ns
t
d(ENL-CLKH)
t
d(CLKL-ENH)
t
W(reg)(min)
delay from enable active to rising clock edge
delay from enable inactive to last falling clock edge
minimum inactive pulse width when consecutively programming
two different registers
minimum inactive pulse width when consecutively programming
two IF divider ratios
minimum inactive pulse width when consecutively programming
two RF divider ratios
enable set-up time to next rising clock edge
40
20
150
ns
ns
ns
t
W(IFLO)(min)
150
ns
t
W(RFLO)(min)
500
ns
t
su(ENH-CLKH)
Register serial input data (pin DATA)
20
ns
t
su(DATA-CLK)
t
h(DATA-CLK)
set-up time DATA to CLK
hold time DATA to CLK
20
20
ns
ns
handbook, full pagewidth
FCA042
MSB
LSB
ACTIVE
INACTIVE
ADDRESS
td(ENL-CLKH)
td(CLKL-ENH)
tsu(ENH-CLKH)
tsu(DATA-CLK)
th(DATA-CLK)
Tcy(CLK)
tr
tf
tW
CLK
DATA
EN
Fig.6 Serial bus timing diagram.
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