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參數(shù)資料
| 型號： | UAA3515AHL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | 900 MHz analog cordless telephone IC |
| 中文描述： | TELECOM, CORDLESS, RF AND BASEBAND CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 X 1.40 MM, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 36/44頁 |
| 文件大?。?/td> | 180K |
| 代理商： | UAA3515AHL |
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2001 Dec 12
36
Philips Semiconductors
Product specification
900 MHz analog cordless telephone IC
UAA3515A
Notes
1.
2.
3.
4.
5.
Measured and guaranteed only on the Philips UAA3515A test board.
Loop filter: C
1
= 1.8 nF; R
2
= 4.7 k
; C
2
= 150 nF (see “Report CTT01001” available on request).
RXAI level will be higher in RX mode than in TX mode.
Loop filter: C
1
= 3.9 nF; R
2
= 6.8 k
; C
2
= 47 nF (see “Report CTT01001” available on request).
Loop filter: C
1
= 470 nF; R
2
= 1.8 k
; C
2
= 4.7
μ
F (see “Report CTT01001” available on request).
Microcontroller interface
DC
CHARACTERISTICS FOR DIGITAL PINS
V
IL
V
IH
LOW-level input voltage
HIGH-level input voltage
serial interface
serial interface
0.5
V
CC
V
V
I
IL
I
IH
LOW-level input current
HIGH-level input current
serial interface; V
IL
= 0.3 V
serial interface;
V
IH
= V
REG
0.3 V
pin CDLBD
pin CDLBD; R
L
= 470 k
5
5
μ
A
μ
A
I
OL
V
OL
V
OH
C
i
C
o
S
ERIAL INTERFACE TIMING
; CLK, DATA and EN (see Fig.10)
LOW-level output current
LOW-level output voltage
HIGH-level output voltage pin CDLBD; R
L
= 470 k
input capacitance
output capacitance
20
0.9V
CC
0.1V
CC
8
8
μ
A
V
V
pF
pF
serial bus
pins RXPD and TXPD
t
su(CLK-EN)
clock to enable set-up
time
input data to clock set-up
time
enable to clock hold time
clock frequency
input rise time
input fall time
delay from last falling
clock edge
enable pulse width
50% signal level
50
ns
t
su(DATA-CLK)
50% signal level
50
ns
t
h(EN-CLK)
f
CLK
t
r
t
f
t
END
50% signal level
50
100
3
50
50
ns
MHz
ns
ns
ns
10% to 90%
10% to 90%
t
w
see Fig.10
ns
t
strt
microcontroller interface
start-up time
90% of V
VREG
to DATA, CLK
and EN present
200
μ
s
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
1.5
----------------
fcomp
-----1
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