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參數(shù)資料
| 型號： | U6812B |
| 廠商： | ATMEL CORP |
| 元件分類： | Line Driver or Receiver |
| 英文描述： | LINE TRANSCEIVER, PDSO16 |
| 封裝： | 0.150 INCH, SOP-16 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 137K |
| 代理商： | U6812B |
5
U6812B
4760A–AUTO–10/03
Application Note
It is recommended to use the external components as shown in Figure 3 on page 3 with
the reverse battery protection diode D
1
and the buffer capacitor C
1
= 10 μF.
Digital Inputs (DIS, IN 1,
IN 2, IN 3 and TxD)
The digital inputs are CMOS-compatible and equipped with a built-in pull-up resistor
with a typical rating of 85 k to V
CC
. The input threshold totals V
TH
= 0.57 V
CC
with a
typical hysteresis of 100 mV. The inputs are designed for an input voltage of -0.2 V to
V
CC
+ 0.6 V.
For proper activation of the output stages, it is mandatory that the inputs are kept low as
long as the supply voltage is not applied. When the supply voltage has been applied, all
inputs need to have a falling edge (see “Timing Diagrams” on page 6).
Digital Output (RxD)
The digital output RxD is a push-pull output stage with a driver power of I
RxD
= 1 mA.
Interference Voltages
and Load Dump (Defined
in DIN40839 or ISO7637)
The U6812B is protected against interference pulses (usually present in the wiring) by
the recommended R
1
C
1
circuitry and the integrated elements (28-V Z-diodes, both at
the supply pin and at the output pins and two diodes connected to V
CC
and GND at the
digital inputs). All transient pulses, which appear on the supply line (V
Batt
), should not
affect the function of the IC (see Table 1).
Table 1.
Transient Test Conditions
Name
Voltage
Source Resistance
Rise Time
Pulse Duration
Pulse Amount
DIN/ISO 1
-110 V
10
100 V/μs
2 ms
15000
DIN/ISO 2
110 V
10
100 V/μs
0.05 ms
15000
DIN/ISO 3a
-160 V
50
30 V/ns
0.1 μs
1 h (reference to ISO)
DIN/ISO 3b
150 V
50
20 V/ns
0.1 μs
1 h (reference to ISO)
DIN/ISO 5
55 V (total)
2
10 V/ms
500 ms
20
Table 2.
Truth Table
WSI-1
WSI-2
WSI-R
EN
TXD
K
WSO-1
WSO-2
WSO-R
RXD
L
L
X
H
X
X
L
L
X
X
H
H
X
X
X
X
Open
Open
X
X
L
L
X
L
X
X
Open
Open
X
X
X
X
H
X
H
Open
X
X
Open
H
X
X
L
X
L
L
L
X
L
L
X
X
X
X
X
H
X
X
X
H
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