- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄381139 > U62256AS2C10 (Electronic Theatre Controls, Inc.) STANDARD 32K X 8 SRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | U62256AS2C10 |
| 廠(chǎng)商： | Electronic Theatre Controls, Inc. |
| 英文描述： | STANDARD 32K X 8 SRAM |
| 中文描述： | 32K的標(biāo)準(zhǔn)× 8的SRAM |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 164K |
| 代理商： | U62256AS2C10 |
U62256A
April 20, 2004
1
!
32768x8 bit static CMOS RAM
!
Access times 70 ns, 100 ns
!
Common data inputs and
data outputs
!
Three-state outputs
!
Typ. operating supply current
70 ns: 50 mA
100 ns: 40 mA
!
TTL/CMOS-compatible
!
Automatical reduction of power
dissipation in long Read Cycles
!
Power supply voltage 5 V + 10 %
!
Operating temperature ranges
0 to
70 °C
-40 to
85 °C
-40 to 125 °C
!
QS 9000 Quality Standard
!
ESD protection > 2000 V
(MIL STD 883C M3015.7)
!
Latch-up immunity >100 mA
!
Packages:
PDIP28 (600 mil)
SOP28 (330 mil)
Standard 32K x 8 SRAM
Features
The U62256A is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at
the outputs DQ0-DQ7. After the
address change, the data outputs
go High-Z until the new information
read is available. The data outputs
have not preferred state.
The Read cycle is finished by the
falling edge of W, or by the rising
edge of E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
Description
Pin Configuration
1
A14
A12
VCC
28
2
W
A13
27
4
A6
A8
25
5
A5
A9
24
3
A7
26
6
A4
A11
23
7
A3
G
A10
22
8
A2
21
12
DQ1
DQ5
17
9
A1
E
DQ7
20
10
A0
19
11
DQ0
DQ6
18
13
DQ2
DQ4
16
14
VSS
DQ3
15
Top View
Signal Name
Signal Description
A0 - A14
DQ0 - DQ7
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
E
G
W
VCC
VSS
Pin Description
PDIP
SOP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| U62256AS2C10G1 | STANDARD 32K X 8 SRAM |
| U62256AS2C10LL | STANDARD 32K X 8 SRAM |
| U62256AS2C10LLG1 | STANDARD 32K X 8 SRAM |
| U62256AS2K07 | STANDARD 32K X 8 SRAM |
| U62256AS2K07G1 | STANDARD 32K X 8 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| U62256AS2C10G1 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:STANDARD 32K X 8 SRAM |
| U62256AS2C10LL | 制造商:ZMD 制造商全稱(chēng):Zentrum Mikroelektronik Dresden AG 功能描述:STANDARD 32K X 8 SRAM |
| U62256AS2C10LLG1 | 制造商:ZMD 制造商全稱(chēng):Zentrum Mikroelektronik Dresden AG 功能描述:STANDARD 32K X 8 SRAM |
| U62256AS2K07 | 制造商:ZMD 制造商全稱(chēng):Zentrum Mikroelektronik Dresden AG 功能描述:STANDARD 32K X 8 SRAM |
| U62256AS2K07G1 | 制造商:ZMD 制造商全稱(chēng):Zentrum Mikroelektronik Dresden AG 功能描述:STANDARD 32K X 8 SRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。