參數(shù)資料
型號(hào): U2391B
英文描述: Quartz Controlled Pulse Generator
中文描述: 石英控制脈沖發(fā)生器
文件頁數(shù): 2/7頁
文件大小: 78K
代理商: U2391B
U2391B
TELEFUNKEN Semiconductors
Rev. A1, 30-May-96
Preliminary Information
2 (7)
Pin Description
Pin
1
2
3
4
5, 6
7
8
Symbol
Period
GND
Output
Contr.
Osc.
Test
V
S
Function
Period selection input
Ground
Output control pulse
Control input
Quartz-oscillator input
Test logic input/output
Supply voltage
1
2
3
4
8
7
6
5
9611805
Period
GND
Output
Contr.
V
S
Test
Osc.
Osc.
Figure 2. Pinning
Description
Pin 1, Period Selection Logic
Period selection at Pin 1 is as follows:
Pin 1 = open,
Pin 1 = ground
Pin 1 = V
S
(Pin 8),
Pin 2, Ground
Pin 3, Output Stage
s
= 1 s
= 60 s
Output stage, being short circuit protected is limited to a
current value of typical 150 mA. Apart from it, there is a
voltage limitation which controls the power stage at the
rate of V
3
28.8 to 32 V and serves as an active Z-diode.
Output pulse width is 31.25 ms when quartz frequency is
32.768 kHz. It is independent of the selected period.
Pin 4, Control Logic
Counting delay is typ 1.5 s (maximum 8 s) when Pin 4
is open and V
S
is switched on.
Programmable residual divider
Pin 4 is connected to Pin 8. This results in an absolute
tolerance, at the start across “Reset/End” to be
Clock input to the 2
7
divider is inhibited, if Pin 4 is
connected to the ground (Pin 2). Absolute tolerance
for every interruption is
1 s is reseated if
1 s.
0.488 ms.
An interruption is ignored (Pin 4 =
put pulse time.
) during the out-
When Pin 4 is switched to V
S
during the output pulse
time
this output pulse will be reseated.
Pin 5, 6 Quartz-Oscillator Input
The propagated period time selection is based on circuit
with a low cost clock quartz of 32.768 kHz.
Pin 7, Test Logic, Figure 2, 3
To test the circuit in a reasonable time, it is possible to
control the divider (f
o
= 16 Hz) at Pin 7 as well as to feed
in a higher frequency to the programmed residual counter
(f
i
2 kHz
).
Pin 8, Supply Voltage
An operating voltage of 4.5 V is necessary for the func-
tioning of the circuit, although an internal switch-on
monitoring allows it to operate with a voltage of 3.6 V.
This means that there is sufficient reliability for the per-
formance of the circuit.
The circuit is designed for 12 V
ply voltage limitation of typical 15 V. In case of higher
voltages there is a need of a series resistance and buffer
capacitance as shown in figure 1.
10% with internal sup-
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