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參數(shù)資料
| 型號(hào)： | TZA1047HL/M2 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.4 MM HEIGHT, PLASTIC, MS-026, SOT314-2, LQFP-64 |
| 文件頁(yè)數(shù)： | 26/69頁(yè) |
| 文件大?。?/td> | 324K |
| 代理商： | TZA1047HL/M2 |
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9397 750 14664
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 1 June 2005
32 of 69
Philips Semiconductors
TZA1047
Preprocessor IC for CD and DVD rewritable
The dropout-concealed scale currents IDOCi are dened as IDOCi = GDOC × INi, where INi
are programmable reference currents (IN1 to IN4) and scale factor GDOC is dened by:
GDOC = 1 if CAN > IT
GDOC = CAN/IT if CAN ≤ IT
where IT is the threshold level for dropout-concealment with which the normalized sum
current CAN is compared. If CAN drops below IT, the scale factor GDOC will decrease
linearly with CAN in order to prevent ‘dividing by zero’. There is a threshold ITW for write
and a threshold ITR for read:IT =ITW if r/w = 0, IT =ITR if r/w = 1. The currents INi,ITW and
ITR are programmable via the I2C-bus.
7.11.3 Focus servo signal block (normalizer sub-block)
The FOC block produces a normalized focus error signal FEN. A detailed block diagram of
the FOC block is shown in Figure 17.
Signal FEN is based on either 2 or 4 input currents selected by bit FEN4/2. Setting
bit FEN4/2 to logic 1 selects all four input currents. The normalizer blocks (N) perform the
same function in the DOC block described in Section 7.11.3. An offset can be applied to
compensate for chromatic aberration in the optics. The offset signal (either OFW or OFR)
is selected by the state of signal r/w; if r/w = 1 (read mode) OFR is used. The polarity of
signal FEN is reversed by setting bit PFEN to logic 1. Signal FEN is available at output D4
by setting bit Q/NE to logic 0, and is also routed to the MON block for test purposes. The
relationship between the FEN signal components is shown in Table 16.
[1]
OF = OFw if r/w = 0, OF = OFR if r/w = 1.
Fig 17. FOC block.
Table 16:
FEN signal (bit PFEN = 0)
Bit FEN4/2
Signal FEN [1]
0
N[Q1, Q3]
× GDOC × IN1 +OF
1
{N[Q1, Q3]
× GDOC × IN1 + N[Q4, Q2] × GDOC × IN1} × 0.5+OF
mce526
0.5
+/
N
IDOC1
FEN4/2
FEN
Q3
Q1
r/w
PFEN
N
IDOC1
OFW
OFR
Q2
Q4
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