參數(shù)資料
型號(hào)： TVP7002PZPR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： GREEN, PLASTIC, HTQFP-100
文件頁(yè)數(shù)： 56/57頁(yè)
文件大?。?/td> 517K
代理商： TVP7002PZPR
SLES206B
– MAY 2007 – REVISED MAY 2011
Electrical Characteristics
IOVDD = 3.3 V, DVDD = 1.9 V, PLL_AVDD = 1.9 V, AVDD = 1.9 V, A33VDD = 3.3 V, TA = 0°C to 70°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
Analog Interface
Input voltage range
By design
0.5
1
2
Vpp
ZI
Input impedance, analog video inputs
By design
500
k
Digital Logic Interface
CI
Input capacitance
By design
10
pF
ZI
Input impedance
By design
500
k
VOH
Output voltage high
IOH = 2 mA
0.8 IOVDD
V
VOL
Output voltage low
IOL = –2 mA
0.2 IOVDD
V
VOH_SCLK
DATACLK output voltage high
IOH = 4 mA
0.8 IOVDD
V
VOL_SCLK
DATACLK output voltage low
IOH = –4 mA
0.2 IOVDD
V
VIH
High-level input voltage
By design
0.7 IOVDD
V
VIL
Low-level input voltage
By design
0.3 IOVDD
V
ADCs
ADC full-scale input range
Clamp disabled
0.95
1
1.05
Vpp
ADC resolution
10-bit range
10
bits
10 bit, 110 MHz, BC = 5
–1
±0.5
+1
DNL
DC differential nonlinearity
LSB
8 bit, 162 MHz, BC = 8
–1
±0.5
+1
10 bit, 110 MHz, BC = 5
–4
±1
+4
INL
DC integral nonlinearity
LSB
8 bit, 162 MHz, BC = 8
–4
±1
+4
10 bit, 110 MHz, BC = 5
none
Missing code
8 bit, 162 MHz, BC = 8
none
SNR
Signal-to-noise ratio
10 MHz, 1 VP-P at 110 MSPS
55
dB
Analog 3-dB bandwidth
By design
350
500
MHz
Horizontal PLL
Clock jitter
500
ps
Phase adjustment
11.6
degree
VCO frequency range
By design
12
162
MHz
Analog ADC Channel
Coarse gain full-scale control range
Gain control value NG = 15
±6
dB
Coarse offset full-scale control range
Referred to 10-bit ADC output
±124
counts
Coarse offset step size
Referred to 10-bit ADC output
4
counts
Sync Processing
Internal clock reference frequency
By design
6.5
MHz
(1)
BC = ADC bias control setting in I2C register, 2Ch
8
Copyright
2007–2011, Texas Instruments Incorporated
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