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參數(shù)資料
| 型號： | TVP7002PZP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | GREEN, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 43/57頁 |
| 文件大小： | 517K |
| 代理商： | TVP7002PZP |
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SLES206B
– MAY 2007 – REVISED MAY 2011
VSYNC Width
Subaddress
3Ch
Read only
7
6
5
4
3
2
1
0
Reserved
VSYNC width [4:0]
VSYNC width [4:0]: Number of lines between the leading and trailing edges of the VSYNC input. The VSYNC width along with the HSYNC
and VSYNC polarities can be used to determine whether the input graphics format is using VESA-CVT generated timings.
NOTE: The VSYNC width counter is not dependent on the H-PLL being locked.
Line Length Tolerance
Subaddress
3Dh
Default (03h)
7
6
5
4
3
2
1
0
Reserved
Line length tolerance [6:0]
Line length tolerance [6:0]: Controls sensitivity to HSYNC input stability when using either the internal or external clock reference. Increased
line length tolerance settings may be required for input signals having horizontal instability. This setting may affect the precison of the clock
cycles per line counter (see subaddresses 39h
–3Ah)
00h = (minimum) tolerance
03h = (default) tolerance
06h = (recommended) tolerance
7Fh = (maximum) tolerance
Reserved
Subaddress
3Eh
Default (04h)
7
6
5
4
3
2
1
0
Reserved [7:0]
Reserved [7:0]:
04h = Required setting (default)
Video Bandwidth Control
Subaddress
3Fh
Default (00h)
7
6
5
4
3
2
1
0
Reserved
BW select [3:0]
BW select [3:0]: Selectable low-pass filter settings for controlling the analog video bandwidth. This control affects the analog video
bandwidth of all three ADC channels.
0h = Highest video bandwidth (default)
Fh = Lowest video bandwidth (~95 MHz analog video bandwidth )
NOTE: This register can be used to filter high frequency noise but lacks the precision for maximum filtering of various video formats. The
lowest bandwidth setting provides a video bandwidth of at least 50 MHz.
AVID Start Pixel
Subaddress
40h
–41h
Default (012Ch)
Subaddress
7
6
5
4
3
2
1
0
40h
AVID start [7:0]
41h
Reserved
AVID active
AVID start [12:8]
AVID active
0 = AVID out active during VBLK (default)
1 = AVID out inactive during VBLK
AVID start [12:0]: AVID start pixel number, this is an absolute pixel location from the leading edge of HSYNC (start pixel 0). The TVP7002
updates the AVID start only when the AVID start MSB byte is written to.
AVID start pixel register also controls the position of SAV code. The TVP7002 inserts the SAV code four pixels before the pixel number
specified in the AVID start pixel register.
48
Copyright
2007–2011, Texas Instruments Incorporated
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參數(shù)描述 |
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| TVP7002PZPR | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 Tr 8/10B 165/110MSPS Video ADC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| TVP9000MZDSR | 制造商:Texas Instruments 功能描述: |
| TVP9000ZDS | 制造商:Texas Instruments 功能描述: |
| TVP9000ZDSR | 制造商:Texas Instruments 功能描述: |
| TVP9001ZDS | 制造商:Texas Instruments 功能描述: |
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