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參數(shù)資料
| 型號(hào)： | TVP7001PZPRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 10/35頁 |
| 文件大?。?/td> | 504K |
| 代理商： | TVP7001PZPRG4 |
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www.ti.com
SLES164 – FEBBRUARY 2006
PLL Divide
Subaddress
01h–02h
Default (69D0h)
7
6
5
4
3
2
1
0
PLL divide MSB [11:4]
PLL divide LSB [3:0]
Reserved
PLL divide [11:0]: PLL divide number sets the number of pixels per line. Controls the PLL feedback divider. MSB [11:4] bits should be loaded
first whenever a change is required
PLL Control
Subaddress
03h
Default (48h)
7
6
5
4
3
2
1
0
VCO[1:0]
Charge Pump Current [2:0]
Reserved
VCO [1:0]: Selects VCO frequency range
00 = Ultra low, less than 20 MHz
01 = Low (default), 20 MHz to 69 MHz
10 = Medium, 70 MHz to 135 MHz
11 = High, 136 MHz to 165 MHz
Charge Pump Current [2:0]: Selects charge current of PLL LPF
000 = Small (default)
111 = Large
Phase Select
Subaddress
04h
Default (80h)
7
6
5
4
3
2
1
0
Phase Select [4:0]
Reserved
DIV2
Phase Select [4:0]: ADC Sampling clock phase select. (1 LSB = 360/32 = 11.25
°)
DATACLK Divide-by-2
0 = DATACLK/1
1 = DATACLK/2
Clamp Start
Subaddress
05h
Default (80h)
7
6
5
4
3
2
1
0
Clamp Start [7:0]
Clamp Start [7:0]: Positions the clamp signal an integer number of clock periods after the HSYNC signal. If external clamping is selected this
value has no meaning. Clamp Start must be correctly positioned for proper operation. See Table 6 for the recommended settings.
Clamp Width
Subaddress
06h
Default (80h)
7
6
5
4
3
2
1
0
Clamp Width [7:0]
Clamp Width [7:0]: Sets the width in pixels for clamp. See register Clamp Start.
Table 6. Recommended Fine Clamp Settings
VIDEO STANDARD
CLAMP WIDTH
HDTV (tri-level)
50 (32h)
32 (20h)
SDTV (bi-level)
6 (06h)
16 (10h)
PC Graphics
6 (06h)
16 (10h)
18
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