參數(shù)資料
型號: TVP6000C
廠商: Texas Instruments, Inc.
英文描述: NTSC/PAL Digital Video Encoder
中文描述: NTSC / PAL數(shù)字視頻編碼器
文件頁數(shù): 17/57頁
文件大?。?/td> 268K
代理商: TVP6000C
2–5
Table 2–1. 16-Bit Video Port YUV 4:2:2
TIME
0
1
2
3
4
5
6
7
VP1[7:0]
Y0
Y1
Y2
Y3
VP2[7:0]
Cb0
Cb1
Cb2
Cb3
Luma pixel number
0
1
2
3
Chroma pixel number
0
2
Table 2–2. 8-Bit Multiplexed Video Port CCIR656 YUV 4:2:2
TIME
0
1
2
3
4
5
6
7
VP1[7:0] or VP2[7:0]
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Luma pixel number
0
1
2
3
Chroma pixel number
0
2
Table 2–3. 100/100 Color Bar in Twos Complement
COLOR
Y (hex)
Cb (hex)
Cr (hex)
White
6B
00
00
Yellow
52
90
12
Cyan
2A
26
90
Green
11
B6
A2
Magenta
EA
4A
5E
Red
D1
DA
70
Blue
A9
70
EE
Black
90
00
00
The SCN bit in the SCM register enables or disables scan conversion. When scan conversion is disabled
(SCN = 0), the input scan lines are interlaced at a field rate of 60 Hz for 525-line systems or 50 Hz for 625-line
systems. When scan conversion is enabled (SCN = 1), the input scan lines are non-interlaced at a frame
rate of 60 Hz or 50 Hz.
2.4
Scaling Processor
The scaling processor scales down the input image in both horizontal and vertical directions. In addition to
scaling, the scaling processor filters the image in the vertical direction and removes annoying flickers, which
are common when a computer-generated graphics or text, especially a static image, is displayed on TV. The
scaling processor uses a 3-tap adaptive filter, whose coefficients are dynamically adjusted on a line-by-line
basis to maintain optimal performance.
The scaling processor is enabled by setting the SCN register bit to 1. When scan conversion is enabled,
the data manager receives non-interlaced pixel data via the demand mode interface and passes pixel data
on to the scaling processor for overscan-compensation processing. The output of the scaling processor
feeds the video encoder core for encoding. See Section 2.5, Video Encoderfor a detailed description.
When the scaling processor is disabled, SCN reset to 0, the data manager receives pixel data via master
or slave mode and passes pixel data directly to the video encoder core, bypassing the scaling processor.
The scaling processor, when enabled, is controlled by the following registers: SPPL, DPPL, SLPF, and
DLPF. These registers define the size of the image before and after scaling. The SPPL register defines the
number of active pixels per line before scaling and the DPPL register defines the number of active pixels
per line after scaling. The SLPF register defines the number of active lines before scaling and the DLPF
register defines the number of active lines after scaling. Refer to Section 2.11, Register Descriptionsfor
additional information on these registers.
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